| /Linux-v5.15/Documentation/devicetree/bindings/mailbox/ |
| D | ti,omap-mailbox.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
26 interrupt configuration registers, and have a rx and tx interrupt source per
28 appropriate programming of the rx and tx interrupt sources on the appropriate
35 lines can also be routed to different processor sub-systems on DRA7xx as they
49 within a SoC. The sub-mailboxes (actual communication channels) are
56 "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
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| D | hisilicon,hi6220-mailbox.txt | 13 --------------------
14 - compatible: Shall be "hisilicon,hi6220-mbox"
15 - reg: Contains the mailbox register address range (base
19 - #mbox-cells: Common mailbox binding property to identify the number
23 slot_id: Slot id used either for TX or RX
26 TX/RX interrupt to application processor,
28 - interrupts: Contains the interrupt information for the mailbox
33 --------------------
34 - hi6220,mbox-tx-noirq: Property of MCU firmware's feature, so mailbox driver
36 flag" mode or IRQ generated mode to acknowledge a TX
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| D | st,stm32-ipcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
16 - Fabien Dessenne <fabien.dessenne@st.com>
17 - Arnaud Pouliquen <arnaud.pouliquen@st.com>
21 const: st,stm32mp1-ipcc
31 - description: rx channel occupied
32 - description: tx channel free
33 - description: wakeup source
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| /Linux-v5.15/arch/arm64/boot/dts/ti/ |
| D | k3-j721e-som-p0.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j721e.dtsi"
18 reserved_memory: reserved-memory {
19 #address-cells = <2>;
20 #size-cells = <2>;
26 no-map;
29 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
30 compatible = "shared-dma-pool";
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| D | k3-j7200-som-p0.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j7200.dtsi"
18 reserved_memory: reserved-memory {
19 #address-cells = <2>;
20 #size-cells = <2>;
26 no-map;
29 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
30 compatible = "shared-dma-pool";
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| D | k3-am642-sk.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include <dt-bindings/mux/ti-serdes.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include "k3-am642.dtsi"
15 compatible = "ti,am642-sk", "ti,am642";
19 stdout-path = "serial2:115200n8";
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| D | k3-am642-evm.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/mux/ti-serdes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include "k3-am642.dtsi"
16 compatible = "ti,am642-evm", "ti,am642";
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| /Linux-v5.15/drivers/firmware/tegra/ |
| D | bpmp-tegra186.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <soc/tegra/bpmp-abi.h>
14 #include "bpmp-private.h"
23 } tx, rx; member
28 } mbox; member
36 priv = container_of(client, struct tegra186_bpmp, mbox.client); in mbox_client_to_bpmp()
38 return priv->parent; in mbox_client_to_bpmp()
45 frame = tegra_ivc_read_get_next_frame(channel->ivc); in tegra186_bpmp_is_message_ready()
47 channel->ib = NULL; in tegra186_bpmp_is_message_ready()
51 channel->ib = frame; in tegra186_bpmp_is_message_ready()
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| /Linux-v5.15/drivers/mailbox/ |
| D | mailbox.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2014 Linaro Ltd.
31 spin_lock_irqsave(&chan->lock, flags); in add_to_rbuf()
34 if (chan->msg_count == MBOX_TX_QUEUE_LEN) { in add_to_rbuf()
35 spin_unlock_irqrestore(&chan->lock, flags); in add_to_rbuf()
36 return -ENOBUFS; in add_to_rbuf()
39 idx = chan->msg_free; in add_to_rbuf()
40 chan->msg_data[idx] = mssg; in add_to_rbuf()
41 chan->msg_count++; in add_to_rbuf()
43 if (idx == MBOX_TX_QUEUE_LEN - 1) in add_to_rbuf()
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| D | hi6220-mailbox.c | 1 // SPDX-License-Identifier: GPL-2.0-only
56 * - direction: tx or rx
57 * - dst irq: peer core's irq number
58 * - ack irq: local irq number
59 * - slot number
72 /* flag of enabling tx's irq mode */
89 static void mbox_set_state(struct hi6220_mbox *mbox, in mbox_set_state() argument
94 status = readl(mbox->base + MBOX_MODE_REG(slot)); in mbox_set_state()
96 writel(status, mbox->base + MBOX_MODE_REG(slot)); in mbox_set_state()
99 static void mbox_set_mode(struct hi6220_mbox *mbox, in mbox_set_mode() argument
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| D | mailbox-sti.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
30 #define STI_IRQ_SET_OFFSET 0x24 /* Generate a Tx channel interrupt */
36 #define MBOX_BASE(mdev, inst) ((mdev)->base + ((inst) * 4))
39 * struct sti_mbox_device - STi Mailbox device data
42 * @mbox: Representation of a communication channel controller
51 * A channel an be used for TX or RX
55 struct mbox_controller *mbox; member
63 * struct sti_mbox_pdata - STi Mailbox platform specific configuration
74 * struct sti_channel - STi Mailbox allocated channel information
88 struct sti_channel *chan_info = chan->con_priv; in sti_mbox_channel_is_enabled()
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| D | zynqmp-ipi-mailbox.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/arm-smccc.h>
15 #include <linux/mailbox/zynqmp-ipi-message.h>
54 #define IPI_MB_CHNL_TX 0 /* IPI mailbox TX channel */
58 * struct zynqmp_ipi_mchan - Description of a Xilinx ZynqMP IPI mailbox channel
78 * struct zynqmp_ipi_mbox - Description of a ZynqMP IPI mailbox
84 * @mbox: mailbox Controller
85 * @mchans: array for channels, tx channel and rx channel.
92 struct mbox_controller mbox; member
97 * struct zynqmp_ipi_pdata - Description of z ZynqMP IPI agent platform data.
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| D | imx-mailbox.c | 1 // SPDX-License-Identifier: GPL-2.0
19 /* TX0/RX0/RXDB[0-3] */
24 IMX_MU_TYPE_TX, /* Tx */
26 IMX_MU_TYPE_TXDB, /* Tx doorbell */
63 struct mbox_controller mbox; member
82 int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data); member
92 #define IMX_MU_xSR_GIPn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
93 #define IMX_MU_xSR_RFn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
94 #define IMX_MU_xSR_TEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
97 #define IMX_MU_xCR_GIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
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| D | arm_mhuv2.c | 1 // SPDX-License-Identifier: GPL-2.0
10 * protocol modes: data-transfer and doorbell, to be used on those channel
19 * hardware - mainly the number of channel windows implemented by the platform,
45 #define LSB_MASK(n) ((1 << (n * __CHAR_BIT__)) - 1)
46 #define MHUV2_PROTOCOL_PROP "arm,mhuv2-protocols"
94 u8 pad1[0x0C - 0x04];
99 u8 pad2[0x20 - 0x1C];
114 u8 pad[0xFC8 - 0xFB0];
124 u8 reserved0[0x10 - 0x0C];
128 u8 pad[0x20 - 0x1C];
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| D | omap-mailbox.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
6 * Copyright (C) 2013-2021 Texas Instruments Incorporated - https://www.ti.com
9 * Suman Anna <s-anna@ti.com>
22 #include <linux/omap-mailbox.h>
68 struct omap_mbox *mbox; member
125 if (!chan || !chan->con_priv) in mbox_chan_to_omap_mbox()
128 return (struct omap_mbox *)chan->con_priv; in mbox_chan_to_omap_mbox()
134 return __raw_readl(mdev->mbox_base + ofs); in mbox_read_reg()
140 __raw_writel(val, mdev->mbox_base + ofs); in mbox_write_reg()
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| /Linux-v5.15/arch/arm/boot/dts/ |
| D | dra72x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
20 compatible = "arm,cortex-a15-pmu";
21 interrupt-parent = <&wakeupgen>;
27 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
28 compatible = "ti,sysc-omap4", "ti,sysc";
31 reg-names = "rev", "sysc";
32 ti,sysc-midle = <SYSC_IDLE_FORCE>,
34 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
37 clock-names = "fck";
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| D | omap2420.dtsi | 4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
18 compatible = "ti,omap2-l4", "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 compatible = "ti,omap2-prcm";
28 #address-cells = <1>;
29 #size-cells = <0>;
37 compatible = "ti,omap2-scm", "simple-bus";
39 #address-cells = <1>;
40 #size-cells = <1>;
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| D | dra74x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
16 compatible = "arm,cortex-a15";
18 operating-points-v2 = <&cpu0_opp_table>;
21 clock-names = "cpu";
23 clock-latency = <300000>; /* From omap-cpufreq driver */
26 #cooling-cells = <2>; /* min followed by max */
28 vbb-supply = <&abb_mpu>;
40 compatible = "arm,cortex-a15-pmu";
41 interrupt-parent = <&wakeupgen>;
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| D | omap2430.dtsi | 4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
18 compatible = "ti,omap2-l4-wkup", "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 compatible = "ti,omap2-prcm";
28 #address-cells = <1>;
29 #size-cells = <0>;
37 compatible = "ti,omap2-scm", "simple-bus";
39 #address-cells = <1>;
40 #size-cells = <1>;
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| /Linux-v5.15/include/linux/ |
| D | mailbox_controller.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
15 * struct mbox_chan_ops - methods to control mailbox channels
16 * @send_data: The API asks the MBOX controller driver, in atomic
18 * data is accepted for transmission, -EBUSY while rejecting
21 * mbox_chan_txdone (if it has some TX ACK irq). It must not
37 * this to poll status of last TX. The controller must
40 * mode 'send_data' is expected to return -EBUSY.
56 * struct mbox_controller - Controller of a class of communication channels
63 * Eg, if it has some TX ACK irq.
64 * @txdone_poll: If the controller can read but not report the TX
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| /Linux-v5.15/drivers/net/ethernet/chelsio/cxgb4/ |
| D | cxgb4.h | 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
62 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
67 /* Suspend an Ethernet Tx queue with fewer available descriptors than this.
138 FEC_RS = 1 << 1, /* Reed-Solomon */
139 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */
213 u64 tx_frames_64; /* # of Tx frames in a particular range */
221 u64 tx_drop; /* # of dropped Tx frames */
262 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
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| /Linux-v5.15/drivers/net/ethernet/marvell/octeontx2/af/ |
| D | mbox.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
34 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
36 #define MBOX_RSP_TIMEOUT 3000 /* Time(ms) to wait for mbox response */
38 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
51 void *mbase; /* This dev's mbox region */
62 void *hwbase; /* Mbox region advertised by HW */
64 u64 trigger; /* Trigger mbox notification */
65 u16 tr_shift; /* Mbox trigger shift */
66 u64 rx_start; /* Offset of Rx region in mbox memory */
67 u64 tx_start; /* Offset of Tx region in mbox memory */
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| /Linux-v5.15/drivers/net/ethernet/marvell/octeontx2/nic/ |
| D | otx2_pf.c | 1 // SPDX-License-Identifier: GPL-2.0
58 netdev->mtu, new_mtu); in otx2_change_mtu()
59 netdev->mtu = new_mtu; in otx2_change_mtu()
69 int irq, vfs = pf->total_vfs; in otx2_disable_flr_me_intr()
73 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); in otx2_disable_flr_me_intr()
78 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); in otx2_disable_flr_me_intr()
84 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); in otx2_disable_flr_me_intr()
85 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); in otx2_disable_flr_me_intr()
88 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); in otx2_disable_flr_me_intr()
89 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); in otx2_disable_flr_me_intr()
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| /Linux-v5.15/drivers/net/wireless/ti/wl12xx/ |
| D | event.c | 1 // SPDX-License-Identifier: GPL-2.0-only
36 struct wl12xx_event_mailbox *mbox = wl->mbox; in wl12xx_process_mailbox_events() local
40 vector = le32_to_cpu(mbox->events_vector); in wl12xx_process_mailbox_events()
41 vector &= ~(le32_to_cpu(mbox->events_mask)); in wl12xx_process_mailbox_events()
43 wl1271_debug(DEBUG_EVENT, "MBOX vector: 0x%x", vector); in wl12xx_process_mailbox_events()
47 mbox->scheduled_scan_status); in wl12xx_process_mailbox_events()
49 if (wl->scan_wlvif) in wl12xx_process_mailbox_events()
50 wl12xx_scan_completed(wl, wl->scan_wlvif); in wl12xx_process_mailbox_events()
56 mbox->scheduled_scan_status); in wl12xx_process_mailbox_events()
63 mbox->scheduled_scan_status); in wl12xx_process_mailbox_events()
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| /Linux-v5.15/Documentation/devicetree/bindings/serial/ |
| D | nvidia,tegra194-tcu.txt | 4 systems within the Tegra SoC. It is implemented through a mailbox-
10 - name : Should be tcu
11 - compatible
14 - "nvidia,tegra194-tcu"
15 - mbox-names:
16 "rx" - Mailbox for receiving data from hardware UART
17 "tx" - Mailbox for transmitting data to hardware UART
18 - mboxes: Mailboxes corresponding to the mbox-names.
24 - .../mailbox/mailbox.txt
25 - .../mailbox/nvidia,tegra186-hsp.txt
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