1 // SPDX-License-Identifier: GPL-2.0
19 /* TX0/RX0/RXDB[0-3] */
24 	IMX_MU_TYPE_TX,		/* Tx */
26 	IMX_MU_TYPE_TXDB,	/* Tx doorbell */
63 	struct mbox_controller	mbox;  member
82 	int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);  member
92 #define IMX_MU_xSR_GIPn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
93 #define IMX_MU_xSR_RFn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
94 #define IMX_MU_xSR_TEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
97 #define IMX_MU_xCR_GIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
99 #define IMX_MU_xCR_RIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
101 #define IMX_MU_xCR_TIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
103 #define IMX_MU_xCR_GIRn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
106 static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)  in to_imx_mu_priv()  argument
108 	return container_of(mbox, struct imx_mu_priv, mbox);  in to_imx_mu_priv()
113 	iowrite32(val, priv->base + offs);  in imx_mu_write()
118 	return ioread32(priv->base + offs);  in imx_mu_read()
126 	spin_lock_irqsave(&priv->xcr_lock, flags);  in imx_mu_xcr_rmw()
127 	val = imx_mu_read(priv, priv->dcfg->xCR[type]);  in imx_mu_xcr_rmw()
130 	imx_mu_write(priv, val, priv->dcfg->xCR[type]);  in imx_mu_xcr_rmw()
131 	spin_unlock_irqrestore(&priv->xcr_lock, flags);  in imx_mu_xcr_rmw()
142 	switch (cp->type) {  in imx_mu_generic_tx()
144 		imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);  in imx_mu_generic_tx()
145 		imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);  in imx_mu_generic_tx()
148 		imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);  in imx_mu_generic_tx()
149 		tasklet_schedule(&cp->txdb_tasklet);  in imx_mu_generic_tx()
152 		dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);  in imx_mu_generic_tx()
153 		return -EINVAL;  in imx_mu_generic_tx()
164 	dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4);  in imx_mu_generic_rx()
165 	mbox_chan_received_data(cp->chan, (void *)&dat);  in imx_mu_generic_rx()
179 	switch (cp->type) {  in imx_mu_scu_tx()
182 		 * msg->hdr.size specifies the number of u32 words while  in imx_mu_scu_tx()
186 		if (msg->hdr.size > sizeof(*msg) / 4) {  in imx_mu_scu_tx()
191 …dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on TX; got: %i bytes\n", sizeof(*msg…  in imx_mu_scu_tx()
192 			return -EINVAL;  in imx_mu_scu_tx()
195 		for (i = 0; i < 4 && i < msg->hdr.size; i++)  in imx_mu_scu_tx()
196 			imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);  in imx_mu_scu_tx()
197 		for (; i < msg->hdr.size; i++) {  in imx_mu_scu_tx()
198 			ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],  in imx_mu_scu_tx()
200 						 xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % 4),  in imx_mu_scu_tx()
203 				dev_err(priv->dev, "Send data index: %d timeout\n", i);  in imx_mu_scu_tx()
206 			imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % 4) * 4);  in imx_mu_scu_tx()
209 		imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);  in imx_mu_scu_tx()
212 		dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);  in imx_mu_scu_tx()
213 		return -EINVAL;  in imx_mu_scu_tx()
227 	imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0));  in imx_mu_scu_rx()
228 	*data++ = imx_mu_read(priv, priv->dcfg->xRR);  in imx_mu_scu_rx()
231 …dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg)…  in imx_mu_scu_rx()
232 		return -EINVAL;  in imx_mu_scu_rx()
236 		ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,  in imx_mu_scu_rx()
237 					 xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0, 100);  in imx_mu_scu_rx()
239 			dev_err(priv->dev, "timeout read idx %d\n", i);  in imx_mu_scu_rx()
242 		*data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);  in imx_mu_scu_rx()
245 	imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);  in imx_mu_scu_rx()
246 	mbox_chan_received_data(cp->chan, (void *)&msg);  in imx_mu_scu_rx()
255 	mbox_chan_txdone(cp->chan, 0);  in imx_mu_txdb_tasklet()
261 	struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);  in imx_mu_isr()
262 	struct imx_mu_con_priv *cp = chan->con_priv;  in imx_mu_isr()
265 	switch (cp->type) {  in imx_mu_isr()
267 		ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);  in imx_mu_isr()
268 		val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);  in imx_mu_isr()
269 		val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) &  in imx_mu_isr()
270 			(ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));  in imx_mu_isr()
273 		ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);  in imx_mu_isr()
274 		val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);  in imx_mu_isr()
275 		val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) &  in imx_mu_isr()
276 			(ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));  in imx_mu_isr()
279 		ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]);  in imx_mu_isr()
280 		val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);  in imx_mu_isr()
281 		val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) &  in imx_mu_isr()
282 			(ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));  in imx_mu_isr()
285 		dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n",  in imx_mu_isr()
286 				     cp->type);  in imx_mu_isr()
293 	if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) &&  in imx_mu_isr()
294 	    (cp->type == IMX_MU_TYPE_TX)) {  in imx_mu_isr()
295 		imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));  in imx_mu_isr()
297 	} else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) &&  in imx_mu_isr()
298 		   (cp->type == IMX_MU_TYPE_RX)) {  in imx_mu_isr()
299 		priv->dcfg->rx(priv, cp);  in imx_mu_isr()
300 	} else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) &&  in imx_mu_isr()
301 		   (cp->type == IMX_MU_TYPE_RXDB)) {  in imx_mu_isr()
302 		imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),  in imx_mu_isr()
303 			     priv->dcfg->xSR[IMX_MU_GSR]);  in imx_mu_isr()
306 		dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");  in imx_mu_isr()
315 	struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);  in imx_mu_send_data()
316 	struct imx_mu_con_priv *cp = chan->con_priv;  in imx_mu_send_data()
318 	return priv->dcfg->tx(priv, cp, data);  in imx_mu_send_data()
323 	struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);  in imx_mu_startup()
324 	struct imx_mu_con_priv *cp = chan->con_priv;  in imx_mu_startup()
328 	pm_runtime_get_sync(priv->dev);  in imx_mu_startup()
329 	if (cp->type == IMX_MU_TYPE_TXDB) {  in imx_mu_startup()
330 		/* Tx doorbell don't have ACK support */  in imx_mu_startup()
331 		tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,  in imx_mu_startup()
337 	if (!priv->dev->pm_domain)  in imx_mu_startup()
340 	ret = request_irq(priv->irq, imx_mu_isr, irq_flag,  in imx_mu_startup()
341 			  cp->irq_desc, chan);  in imx_mu_startup()
343 		dev_err(priv->dev,  in imx_mu_startup()
344 			"Unable to acquire IRQ %d\n", priv->irq);  in imx_mu_startup()
348 	switch (cp->type) {  in imx_mu_startup()
350 		imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0);  in imx_mu_startup()
353 		imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0);  in imx_mu_startup()
364 	struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);  in imx_mu_shutdown()
365 	struct imx_mu_con_priv *cp = chan->con_priv;  in imx_mu_shutdown()
367 	if (cp->type == IMX_MU_TYPE_TXDB) {  in imx_mu_shutdown()
368 		tasklet_kill(&cp->txdb_tasklet);  in imx_mu_shutdown()
369 		pm_runtime_put_sync(priv->dev);  in imx_mu_shutdown()
373 	switch (cp->type) {  in imx_mu_shutdown()
375 		imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));  in imx_mu_shutdown()
378 		imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));  in imx_mu_shutdown()
381 		imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));  in imx_mu_shutdown()
387 	free_irq(priv->irq, chan);  in imx_mu_shutdown()
388 	pm_runtime_put_sync(priv->dev);  in imx_mu_shutdown()
397 static struct mbox_chan *imx_mu_scu_xlate(struct mbox_controller *mbox,  in imx_mu_scu_xlate()  argument
402 	if (sp->args_count != 2) {  in imx_mu_scu_xlate()
403 		dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);  in imx_mu_scu_xlate()
404 		return ERR_PTR(-EINVAL);  in imx_mu_scu_xlate()
407 	type = sp->args[0]; /* channel type */  in imx_mu_scu_xlate()
408 	idx = sp->args[1]; /* index */  in imx_mu_scu_xlate()
414 			dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);  in imx_mu_scu_xlate()
421 		dev_err(mbox->dev, "Invalid chan type: %d\n", type);  in imx_mu_scu_xlate()
422 		return ERR_PTR(-EINVAL);  in imx_mu_scu_xlate()
425 	if (chan >= mbox->num_chans) {  in imx_mu_scu_xlate()
426 		dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);  in imx_mu_scu_xlate()
427 		return ERR_PTR(-EINVAL);  in imx_mu_scu_xlate()
430 	return &mbox->chans[chan];  in imx_mu_scu_xlate()
433 static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,  in imx_mu_xlate()  argument
438 	if (sp->args_count != 2) {  in imx_mu_xlate()
439 		dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);  in imx_mu_xlate()
440 		return ERR_PTR(-EINVAL);  in imx_mu_xlate()
443 	type = sp->args[0]; /* channel type */  in imx_mu_xlate()
444 	idx = sp->args[1]; /* index */  in imx_mu_xlate()
447 	if (chan >= mbox->num_chans) {  in imx_mu_xlate()
448 		dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);  in imx_mu_xlate()
449 		return ERR_PTR(-EINVAL);  in imx_mu_xlate()
452 	return &mbox->chans[chan];  in imx_mu_xlate()
460 		struct imx_mu_con_priv *cp = &priv->con_priv[i];  in imx_mu_init_generic()
462 		cp->idx = i % 4;  in imx_mu_init_generic()
463 		cp->type = i >> 2;  in imx_mu_init_generic()
464 		cp->chan = &priv->mbox_chans[i];  in imx_mu_init_generic()
465 		priv->mbox_chans[i].con_priv = cp;  in imx_mu_init_generic()
466 		snprintf(cp->irq_desc, sizeof(cp->irq_desc),  in imx_mu_init_generic()
467 			 "imx_mu_chan[%i-%i]", cp->type, cp->idx);  in imx_mu_init_generic()
470 	priv->mbox.num_chans = IMX_MU_CHANS;  in imx_mu_init_generic()
471 	priv->mbox.of_xlate = imx_mu_xlate;  in imx_mu_init_generic()
473 	if (priv->side_b)  in imx_mu_init_generic()
478 		imx_mu_write(priv, 0, priv->dcfg->xCR[i]);  in imx_mu_init_generic()
486 		struct imx_mu_con_priv *cp = &priv->con_priv[i];  in imx_mu_init_scu()
488 		cp->idx = i < 2 ? 0 : i - 2;  in imx_mu_init_scu()
489 		cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;  in imx_mu_init_scu()
490 		cp->chan = &priv->mbox_chans[i];  in imx_mu_init_scu()
491 		priv->mbox_chans[i].con_priv = cp;  in imx_mu_init_scu()
492 		snprintf(cp->irq_desc, sizeof(cp->irq_desc),  in imx_mu_init_scu()
493 			 "imx_mu_chan[%i-%i]", cp->type, cp->idx);  in imx_mu_init_scu()
496 	priv->mbox.num_chans = IMX_MU_SCU_CHANS;  in imx_mu_init_scu()
497 	priv->mbox.of_xlate = imx_mu_scu_xlate;  in imx_mu_init_scu()
501 		imx_mu_write(priv, 0, priv->dcfg->xCR[i]);  in imx_mu_init_scu()
506 	struct device *dev = &pdev->dev;  in imx_mu_probe()
507 	struct device_node *np = dev->of_node;  in imx_mu_probe()
514 		return -ENOMEM;  in imx_mu_probe()
516 	priv->dev = dev;  in imx_mu_probe()
518 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in imx_mu_probe()
519 	if (IS_ERR(priv->base))  in imx_mu_probe()
520 		return PTR_ERR(priv->base);  in imx_mu_probe()
522 	priv->irq = platform_get_irq(pdev, 0);  in imx_mu_probe()
523 	if (priv->irq < 0)  in imx_mu_probe()
524 		return priv->irq;  in imx_mu_probe()
528 		return -EINVAL;  in imx_mu_probe()
529 	priv->dcfg = dcfg;  in imx_mu_probe()
531 	priv->clk = devm_clk_get(dev, NULL);  in imx_mu_probe()
532 	if (IS_ERR(priv->clk)) {  in imx_mu_probe()
533 		if (PTR_ERR(priv->clk) != -ENOENT)  in imx_mu_probe()
534 			return PTR_ERR(priv->clk);  in imx_mu_probe()
536 		priv->clk = NULL;  in imx_mu_probe()
539 	ret = clk_prepare_enable(priv->clk);  in imx_mu_probe()
545 	priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");  in imx_mu_probe()
547 	priv->dcfg->init(priv);  in imx_mu_probe()
549 	spin_lock_init(&priv->xcr_lock);  in imx_mu_probe()
551 	priv->mbox.dev = dev;  in imx_mu_probe()
552 	priv->mbox.ops = &imx_mu_ops;  in imx_mu_probe()
553 	priv->mbox.chans = priv->mbox_chans;  in imx_mu_probe()
554 	priv->mbox.txdone_irq = true;  in imx_mu_probe()
558 	ret = devm_mbox_controller_register(dev, &priv->mbox);  in imx_mu_probe()
560 		clk_disable_unprepare(priv->clk);  in imx_mu_probe()
576 	clk_disable_unprepare(priv->clk);  in imx_mu_probe()
582 	clk_disable_unprepare(priv->clk);  in imx_mu_probe()
590 	pm_runtime_disable(priv->dev);  in imx_mu_remove()
596 	.tx	= imx_mu_generic_tx,
606 	.tx	= imx_mu_generic_tx,
616 	.tx	= imx_mu_generic_tx,
627 	.tx	= imx_mu_scu_tx,
637 	{ .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
638 	{ .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
639 	{ .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
640 	{ .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
650 	if (!priv->clk) {  in imx_mu_suspend_noirq()
652 			priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]);  in imx_mu_suspend_noirq()
671 	if (!imx_mu_read(priv, priv->dcfg->xCR[0]) && !priv->clk) {  in imx_mu_resume_noirq()
673 			imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]);  in imx_mu_resume_noirq()
683 	clk_disable_unprepare(priv->clk);  in imx_mu_runtime_suspend()
693 	ret = clk_prepare_enable(priv->clk);  in imx_mu_runtime_resume()