Home
last modified time | relevance | path

Searched +full:m +full:- +full:phy (Results 1 – 25 of 529) sorted by relevance

12345678910>>...22

/Linux-v5.10/drivers/staging/greybus/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
11 To compile this code as a module, chose M here: the module
12 will be called gb-audio.ko
20 bridge from an APB-I2S port to a Unipro network.
22 To compile this code as a module, chose M here: the module
23 will be called gb-audio-codec.ko
32 To compile this code as a module, chose M here: the module
33 will be called gb-bootrom.ko
42 To compile this code as a module, chose M here: the module
43 will be called gb-camera.ko
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/phy/
Dphy-mtk-ufs.txt1 MediaTek Universal Flash Storage (UFS) M-PHY binding
2 --------------------------------------------------------
4 UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
5 Each UFS M-PHY node should have its own node.
7 To bind UFS M-PHY with UFS host controller, the controller node should
8 contain a phandle reference to UFS M-PHY node.
10 Required properties for UFS M-PHY nodes:
11 - compatible : Compatible list, contains the following controller:
12 "mediatek,mt8183-ufsphy" for ufs phy
14 - reg : Address and length of the UFS M-PHY register set.
[all …]
Dphy-rockchip-inno-usb2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip USB2.0 phy with inno IP block
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-usb2phy
16 - rockchip,rk3228-usb2phy
17 - rockchip,rk3328-usb2phy
18 - rockchip,rk3366-usb2phy
[all …]
Dphy-mtk-tphy.txt1 MediaTek T-PHY binding
2 --------------------------
4 T-phy controller supports physical layer functionality for a number of
8 - compatible : should be one of
9 "mediatek,generic-tphy-v1"
10 "mediatek,generic-tphy-v2"
11 "mediatek,mt2701-u3phy" (deprecated)
12 "mediatek,mt2712-u3phy" (deprecated)
13 "mediatek,mt8173-u3phy";
14 make use of "mediatek,generic-tphy-v1" on mt2701 instead and
[all …]
Dphy-mtk-xsphy.txt1 MediaTek XS-PHY binding
2 --------------------------
4 The XS-PHY controller supports physical layer functionality for USB3.1
8 - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
9 soc-model is the name of SoC, such as mt3611 etc;
12 - "mediatek,mt3611-xsphy"
14 - #address-cells, #size-cells : should use the same values as the root node
15 - ranges: must be present
18 - reg : offset and length of register shared by multiple U3 ports,
21 - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
[all …]
Drockchip-dp-phy.txt1 Rockchip specific extensions to the Analogix Display Port PHY
2 ------------------------------------
5 - compatible : should be one of the following supported values:
6 - "rockchip.rk3288-dp-phy"
7 - clocks: from common clock binding: handle to dp clock.
9 - clock-names: from common clock binding:
10 Required elements: "24m"
11 - #phy-cells : from the generic PHY bindings, must be 0;
16 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
20 edp_phy: edp-phy {
[all …]
/Linux-v5.10/drivers/char/tpm/
Dtpm_tis_spi_main.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Christophe Ricard <christophe-h.ricard@st.com>
10 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
46 * [1] https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/
48 static int tpm_tis_spi_flow_control(struct tpm_tis_spi_phy *phy, in tpm_tis_spi_flow_control() argument
51 struct spi_message m; in tpm_tis_spi_flow_control() local
54 if ((phy->iobuf[3] & 0x01) == 0) { in tpm_tis_spi_flow_control()
57 spi_xfer->len = 1; in tpm_tis_spi_flow_control()
58 spi_message_init(&m); in tpm_tis_spi_flow_control()
59 spi_message_add_tail(spi_xfer, &m); in tpm_tis_spi_flow_control()
[all …]
Dtpm_tis_spi_cr50.c1 // SPDX-License-Identifier: GPL-2.0
23 * - can go to sleep not earlier than after CR50_SLEEP_DELAY_MSEC.
24 * - needs up to CR50_WAKE_START_DELAY_USEC to wake after sleep.
25 * - requires waiting for "ready" IRQ, if supported; or waiting for at least
27 * - waits for up to CR50_FLOW_CONTROL for flow control 'ready' indication.
52 static inline struct cr50_spi_phy *to_cr50_spi_phy(struct tpm_tis_spi_phy *phy) in to_cr50_spi_phy() argument
54 return container_of(phy, struct cr50_spi_phy, spi_phy); in to_cr50_spi_phy()
66 cr50_phy->irq_confirmed = true; in cr50_spi_irq_handler()
67 complete(&cr50_phy->spi_phy.ready); in cr50_spi_irq_handler()
76 static void cr50_ensure_access_delay(struct cr50_spi_phy *phy) in cr50_ensure_access_delay() argument
[all …]
/Linux-v5.10/drivers/usb/phy/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
26 depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, this can't be 'y'
35 depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, this can't be 'y'
39 USB-On-The-Go transceiver working with the OMAP OTG controller.
45 will be called phy-isp1301-omap.
48 tristate "Keystone USB PHY Driver"
52 Enable this to support Keystone USB phy. This driver provides
53 interface to interact with USB 2.0 and USB 3.0 PHY that is part
58 depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, NOP can't be built-in
62 built-in with usb ip or which are autonomous and doesn't require any
[all …]
/Linux-v5.10/drivers/gpu/drm/sun4i/
Dsun8i_hdmi_phy_clk.c1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/clk-provider.h>
12 struct sun8i_hdmi_phy *phy; member
23 unsigned long rate = req->rate; in sun8i_phy_clk_determine_rate()
49 abs(rate - rounded / i) < in sun8i_phy_clk_determine_rate()
50 abs(rate - best_rate / best_div)) { in sun8i_phy_clk_determine_rate()
61 req->rate = best_rate / best_div; in sun8i_phy_clk_determine_rate()
62 req->best_parent_rate = best_rate; in sun8i_phy_clk_determine_rate()
63 req->best_parent_hw = best_parent; in sun8i_phy_clk_determine_rate()
74 regmap_read(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG, &reg); in sun8i_phy_clk_recalc_rate()
[all …]
/Linux-v5.10/drivers/phy/marvell/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Marvell platforms
12 tristate "Marvell Berlin SATA PHY driver"
17 Enable this to support the SATA PHY on Marvell Berlin SoCs.
20 tristate "Marvell Berlin USB PHY Driver"
25 Enable this to support the USB PHY on Marvell Berlin SoCs.
46 Enable this to support Marvell A3700 UTMI PHY driver.
77 tristate "Marvell USB HSIC 28nm PHY Driver"
81 Enable this to support Marvell USB HSIC PHY driver for Marvell
82 SoC. This driver will do the PHY initialization and shutdown.
[all …]
/Linux-v5.10/drivers/phy/mediatek/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Mediatek devices
6 tristate "MediaTek T-PHY Driver"
11 Say 'Y' here to add support for MediaTek T-PHY driver,
13 SATA, and meanwhile supports two version T-PHY which have
14 different banks layout, the T-PHY with shared banks between
15 multi-ports is first version, otherwise is second version,
19 tristate "MediaTek UFS M-PHY driver"
24 Support for UFS M-PHY on MediaTek chipsets.
25 Enable this to provide vendor-specific probing,
[all …]
/Linux-v5.10/drivers/phy/qualcomm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Qualcomm and Atheros platforms
6 tristate "Atheros AR71XX/9XXX USB PHY driver"
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
15 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
22 tristate "Qualcomm IPQ4019 USB PHY driver"
26 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
29 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
36 tristate "Qualcomm PCIe Gen2 PHY Driver"
40 Enable this to support the Qualcomm PCIe PHY, used with the Synopsys
[all …]
/Linux-v5.10/drivers/net/fddi/skfp/
Dsmt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
26 #define m_fc(mb) ((mb)->sm_data[0])
55 static int phy_index(struct s_smc *smc, int phy);
57 static int phy_con_resource_index(struct s_smc *smc, int phy);
82 static void smt_fill_lem(struct s_smc *smc, struct smt_p_lem *lem, int phy);
111 return(*(short *)(&addr->a[0]) == in is_my_addr()
112 *(short *)(&smc->mib.m[MAC0].fddiMACSMTAddress.a[0]) in is_my_addr()
113 && *(short *)(&addr->a[2]) == in is_my_addr()
114 *(short *)(&smc->mib.m[MAC0].fddiMACSMTAddress.a[2]) in is_my_addr()
115 && *(short *)(&addr->a[4]) == in is_my_addr()
[all …]
/Linux-v5.10/drivers/phy/hisilicon/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Hisilicon platforms
6 tristate "hi6220 USB PHY support"
12 Enable this to support the HISILICON HI6220 USB PHY.
14 To compile this driver as a module, choose M here.
17 tristate "hi3660 USB PHY support"
22 Enable this to support the HISILICON HI3660 USB PHY.
24 To compile this driver as a module, choose M here.
36 tristate "HiSilicon INNO USB2 PHY support"
41 Support for INNO USB2 PHY on HiSilicon SoCs. This Phy supports
[all …]
/Linux-v5.10/drivers/scsi/bfa/
Dbfa_ioc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
4 * Copyright (c) 2014- QLogic Corporation.
8 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
31 bfa_timer_begin((__ioc)->timer_mod, &(__ioc)->ioc_timer, \
33 #define bfa_ioc_timer_stop(__ioc) bfa_timer_stop(&(__ioc)->ioc_timer)
36 bfa_timer_begin((__ioc)->timer_mod, &(__ioc)->hb_timer, \
38 #define bfa_hb_timer_stop(__ioc) bfa_timer_stop(&(__ioc)->hb_timer)
55 ((__ioc)->ioc_hwif->ioc_firmware_lock(__ioc))
57 ((__ioc)->ioc_hwif->ioc_firmware_unlock(__ioc))
[all …]
/Linux-v5.10/drivers/phy/rockchip/
Dphy-rockchip-dp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip DP PHY driver
6 * Author: Yakir Yang <ykk@@rock-chips.com>
13 #include <linux/phy/phy.h>
32 static int rockchip_set_phy_state(struct phy *phy, bool enable) in rockchip_set_phy_state() argument
34 struct rockchip_dp_phy *dp = phy_get_drvdata(phy); in rockchip_set_phy_state()
38 ret = regmap_write(dp->grf, GRF_SOC_CON12, in rockchip_set_phy_state()
42 dev_err(dp->dev, "Can't enable PHY power %d\n", ret); in rockchip_set_phy_state()
46 ret = clk_prepare_enable(dp->phy_24m); in rockchip_set_phy_state()
48 clk_disable_unprepare(dp->phy_24m); in rockchip_set_phy_state()
[all …]
/Linux-v5.10/drivers/net/ethernet/wiznet/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
27 PHY and hardware TCP/IP stack, but this driver is limited to
28 the MAC and PHY functions only, onchip TCP/IP is unused.
30 To compile this driver as a module, choose M here: the module
40 PHY and hardware TCP/IP stack, but this driver is limited to
41 the MAC and PHY functions only, onchip TCP/IP is unused.
43 To compile this driver as a module, choose M here: the module
55 after mapping to Memory-Mapped I/O space.
62 which are directly mapped to Memory-Mapped I/O space.
84 To compile this driver as a module, choose M here: the module
[all …]
/Linux-v5.10/drivers/usb/common/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
14 Say Y here if you are working on a system with led-class supported
19 tristate "USB ULPI PHY interface support"
23 USB 2.0 PHY interface. The ULPI specification defines a standard set
29 controllers which support ULPI register access and have ULPI PHY
30 attached to them. The ULPI PHY drivers themselves are normal PHY
36 To compile this driver as a module, choose M here: the module will
51 To compile the driver as a module, choose M here: the module will
52 be called usb-conn-gpio.ko
/Linux-v5.10/drivers/phy/samsung/
Dphy-samsung-ufs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * UFS PHY driver for Samsung EXYNOS SoC
35 /* UFS PHY registers */
42 /* description for PHY calibration */
71 #define PWR_MODE(g, s, m) ((((g) & GR_MASK) << 4) |\ argument
72 (((s) & SR_MASK) << 2) | ((m) & MD_MASK))
81 /* PHY calibration point/state */
125 static inline struct samsung_ufs_phy *get_samsung_ufs_phy(struct phy *phy) in get_samsung_ufs_phy() argument
127 return (struct samsung_ufs_phy *)phy_get_drvdata(phy); in get_samsung_ufs_phy()
131 struct samsung_ufs_phy *phy, u32 isol) in samsung_ufs_phy_ctrl_isol() argument
[all …]
/Linux-v5.10/drivers/gpio/
Dgpio-stp-xway.c1 // SPDX-License-Identifier: GPL-2.0-only
74 #define xway_stp_r32(m, reg) __raw_readl(m + reg) argument
75 #define xway_stp_w32(m, val, reg) __raw_writel(val, m + reg) argument
76 #define xway_stp_w32_mask(m, clear, set, reg) \ argument
77 xway_stp_w32(m, (xway_stp_r32(m, reg) & ~(clear)) | (set), reg)
84 u8 groups; /* we can drive 1-3 groups of 8bit each */
94 * xway_stp_get() - gpio_chip->get - get gpios.
104 return (xway_stp_r32(chip->virt, XWAY_STP_CPU0) & BIT(gpio)); in xway_stp_get()
108 * xway_stp_set() - gpio_chip->set - set gpios.
120 chip->shadow |= BIT(gpio); in xway_stp_set()
[all …]
/Linux-v5.10/drivers/net/wireless/mediatek/mt76/mt7915/
Dmt7915.h1 /* SPDX-License-Identifier: ISC */
15 #define MT7915_WTBL_RESERVED (MT7915_WTBL_SIZE - 1)
16 #define MT7915_WTBL_STA (MT7915_WTBL_RESERVED - \
36 #define MT7915_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */
37 #define MT7915_CFEND_RATE_11B 0x03 /* 11B LP, 11M */
38 #define MT7915_5G_RATE_DEFAULT 0x4b /* OFDM 6M */
39 #define MT7915_2G_RATE_DEFAULT 0x0 /* CCK 1M */
96 struct mt7915_phy *phy; member
145 struct mt7915_phy phy; member
235 struct mt76_phy *phy = hw->priv; in mt7915_hw_phy() local
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/ufs/
Dufs-mediatek.txt3 UFS nodes are defined to describe on-chip UFS hardware macro.
6 To bind UFS PHY with UFS host controller, the controller node should
7 contain a phandle reference to UFS M-PHY node.
10 - compatible : Compatible list, contains the following controller:
11 "mediatek,mt8183-ufshci" for MediaTek UFS host controller
13 "mediatek,mt8192-ufshci" for MediaTek UFS host controller
15 - reg : Address and length of the UFS register set.
16 - phys : phandle to m-phy.
17 - clocks : List of phandle and clock specifier pairs.
18 - clock-names : List of clock input name strings sorted in the same
[all …]
/Linux-v5.10/drivers/net/ethernet/ti/
Dcpsw_ethtool.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/phy.h>
75 #define CPSW_STAT(m) CPSW_STATS, \ argument
76 sizeof_field(struct cpsw_hw_stats, m), \
77 offsetof(struct cpsw_hw_stats, m)
78 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ argument
79 sizeof_field(struct cpdma_chan_stats, m), \
80 offsetof(struct cpdma_chan_stats, m)
81 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ argument
82 sizeof_field(struct cpdma_chan_stats, m), \
[all …]
/Linux-v5.10/drivers/phy/mscc/
Dphy-ocelot-serdes.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * SerDes PHY driver for Microsemi Ocelot
14 #include <linux/phy.h>
15 #include <linux/phy/phy.h>
19 #include <dt-bindings/phy/phy-ocelot-serdes.h>
24 struct phy *phys[SERDES_MAX];
354 #define SERDES_MUX_SGMII(i, p, m, c) \ argument
355 SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_SGMII, m, c)
356 #define SERDES_MUX_QSGMII(i, p, m, c) \ argument
357 SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_QSGMII, m, c)
[all …]

12345678910>>...22