1 // SPDX-License-Identifier: GPL-2.0-only
74 #define xway_stp_r32(m, reg)		__raw_readl(m + reg)  argument
75 #define xway_stp_w32(m, val, reg)	__raw_writel(val, m + reg)  argument
76 #define xway_stp_w32_mask(m, clear, set, reg) \  argument
77 		xway_stp_w32(m, (xway_stp_r32(m, reg) & ~(clear)) | (set), reg)
84 	u8 groups;	/* we can drive 1-3 groups of 8bit each */
94  * xway_stp_get() - gpio_chip->get - get gpios.
104 	return (xway_stp_r32(chip->virt, XWAY_STP_CPU0) & BIT(gpio));  in xway_stp_get()
108  * xway_stp_set() - gpio_chip->set - set gpios.
120 		chip->shadow |= BIT(gpio);  in xway_stp_set()
122 		chip->shadow &= ~BIT(gpio);  in xway_stp_set()
123 	xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0);  in xway_stp_set()
124 	if (!chip->reserved)  in xway_stp_set()
125 		xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0);  in xway_stp_set()
129  * xway_stp_dir_out() - gpio_chip->dir_out - set gpio direction.
144  * xway_stp_request() - gpio_chip->request
154 	if ((gpio < 8) && (chip->reserved & BIT(gpio))) {  in xway_stp_request()
155 		dev_err(gc->parent, "GPIO %d is driven by hardware\n", gpio);  in xway_stp_request()
156 		return -ENODEV;  in xway_stp_request()
163  * xway_stp_hw_init() - Configure the STP unit and enable the clock gate
169 	xway_stp_w32(chip->virt, 0, XWAY_STP_AR);  in xway_stp_hw_init()
170 	xway_stp_w32(chip->virt, 0, XWAY_STP_CPU0);  in xway_stp_hw_init()
171 	xway_stp_w32(chip->virt, 0, XWAY_STP_CPU1);  in xway_stp_hw_init()
172 	xway_stp_w32(chip->virt, XWAY_STP_CON_SWU, XWAY_STP_CON0);  in xway_stp_hw_init()
173 	xway_stp_w32(chip->virt, 0, XWAY_STP_CON1);  in xway_stp_hw_init()
176 	xway_stp_w32_mask(chip->virt, XWAY_STP_EDGE_MASK,  in xway_stp_hw_init()
177 				chip->edge, XWAY_STP_CON0);  in xway_stp_hw_init()
180 	xway_stp_w32_mask(chip->virt, XWAY_STP_GROUP_MASK,  in xway_stp_hw_init()
181 				chip->groups, XWAY_STP_CON1);  in xway_stp_hw_init()
184 	xway_stp_w32_mask(chip->virt,  in xway_stp_hw_init()
186 			chip->dsl << XWAY_STP_ADSL_SHIFT,  in xway_stp_hw_init()
190 	xway_stp_w32_mask(chip->virt,  in xway_stp_hw_init()
192 			chip->phy1 << XWAY_STP_PHY1_SHIFT,  in xway_stp_hw_init()
194 	xway_stp_w32_mask(chip->virt,  in xway_stp_hw_init()
196 			chip->phy2 << XWAY_STP_PHY2_SHIFT,  in xway_stp_hw_init()
201 		xway_stp_w32_mask(chip->virt,  in xway_stp_hw_init()
203 				chip->phy3 << XWAY_STP_PHY3_SHIFT,  in xway_stp_hw_init()
208 		xway_stp_w32_mask(chip->virt,  in xway_stp_hw_init()
210 				chip->phy4 << XWAY_STP_PHY4_SHIFT,  in xway_stp_hw_init()
215 	chip->reserved = (chip->phy4 << 11) | (chip->phy3 << 8) | (chip->phy2 << 5)  in xway_stp_hw_init()
216 		| (chip->phy1 << 2) | chip->dsl;  in xway_stp_hw_init()
222 	if (chip->reserved) {  in xway_stp_hw_init()
223 		xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK,  in xway_stp_hw_init()
225 		xway_stp_w32_mask(chip->virt, XWAY_STP_SPEED_MASK,  in xway_stp_hw_init()
227 		xway_stp_w32_mask(chip->virt, XWAY_STP_FPIS_MASK,  in xway_stp_hw_init()
234 	u32 shadow, groups, dsl, phy;  in xway_stp_probe()  local
239 	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);  in xway_stp_probe()
241 		return -ENOMEM;  in xway_stp_probe()
243 	chip->virt = devm_platform_ioremap_resource(pdev, 0);  in xway_stp_probe()
244 	if (IS_ERR(chip->virt))  in xway_stp_probe()
245 		return PTR_ERR(chip->virt);  in xway_stp_probe()
247 	chip->gc.parent = &pdev->dev;  in xway_stp_probe()
248 	chip->gc.label = "stp-xway";  in xway_stp_probe()
249 	chip->gc.direction_output = xway_stp_dir_out;  in xway_stp_probe()
250 	chip->gc.get = xway_stp_get;  in xway_stp_probe()
251 	chip->gc.set = xway_stp_set;  in xway_stp_probe()
252 	chip->gc.request = xway_stp_request;  in xway_stp_probe()
253 	chip->gc.base = -1;  in xway_stp_probe()
254 	chip->gc.owner = THIS_MODULE;  in xway_stp_probe()
257 	if (!of_property_read_u32(pdev->dev.of_node, "lantiq,shadow", &shadow))  in xway_stp_probe()
258 		chip->shadow = shadow;  in xway_stp_probe()
261 	if (!of_property_read_u32(pdev->dev.of_node, "lantiq,groups", &groups))  in xway_stp_probe()
262 		chip->groups = groups & XWAY_STP_GROUP_MASK;  in xway_stp_probe()
264 		chip->groups = XWAY_STP_GROUP0;  in xway_stp_probe()
265 	chip->gc.ngpio = fls(chip->groups) * 8;  in xway_stp_probe()
268 	if (!of_property_read_u32(pdev->dev.of_node, "lantiq,dsl", &dsl))  in xway_stp_probe()
269 		chip->dsl = dsl & XWAY_STP_ADSL_MASK;  in xway_stp_probe()
277 		if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy1", &phy))  in xway_stp_probe()
278 			chip->phy1 = phy & XWAY_STP_PHY_MASK;  in xway_stp_probe()
279 		if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy2", &phy))  in xway_stp_probe()
280 			chip->phy2 = phy & XWAY_STP_PHY_MASK;  in xway_stp_probe()
285 		if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy3", &phy))  in xway_stp_probe()
286 			chip->phy3 = phy & XWAY_STP_PHY_MASK;  in xway_stp_probe()
290 		if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy4", &phy))  in xway_stp_probe()
291 			chip->phy4 = phy & XWAY_STP_PHY_MASK;  in xway_stp_probe()
295 	if (!of_find_property(pdev->dev.of_node, "lantiq,rising", NULL))  in xway_stp_probe()
296 		chip->edge = XWAY_STP_FALLING;  in xway_stp_probe()
298 	clk = devm_clk_get(&pdev->dev, NULL);  in xway_stp_probe()
300 		dev_err(&pdev->dev, "Failed to get clock\n");  in xway_stp_probe()
310 	ret = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);  in xway_stp_probe()
316 	dev_info(&pdev->dev, "Init done\n");  in xway_stp_probe()
322 	{ .compatible = "lantiq,gpio-stp-xway" },
330 		.name = "gpio-stp-xway",