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/Linux-v6.1/kernel/locking/
Dlock_events_list.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 LOCK_EVENT(pv_latency_kick) /* Average latency (ns) of vCPU kick */
29 LOCK_EVENT(pv_latency_wake) /* Average latency (ns) of kick-to-wakeup */
30 LOCK_EVENT(pv_lock_stealing) /* # of lock stealing operations */
31 LOCK_EVENT(pv_spurious_wakeup) /* # of spurious wakeups in non-head vCPUs */
35 LOCK_EVENT(pv_wait_node) /* # of vCPU wait's at non-head queue node */
45 LOCK_EVENT(lock_slowpath) /* # of locking ops via MCS lock queue */
59 LOCK_EVENT(rwsem_opt_lock) /* # of opt-acquired write locks */
63 LOCK_EVENT(rwsem_rlock_steal) /* # of read locks by lock stealing */
65 LOCK_EVENT(rwsem_rlock_fail) /* # of failed read lock acquisitions */
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/Linux-v6.1/Documentation/devicetree/bindings/opp/
Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
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/Linux-v6.1/drivers/gpu/drm/i915/gt/
Dintel_rc6.c1 // SPDX-License-Identifier: MIT
24 * low-voltage mode when idle, using down to 0V while at this stage. This
30 * among each other with the latency required to enter and leave RC6 and
38 * require higher latency to switch to and wake up.
48 return rc6_to_gt(rc)->uncore; in rc6_to_uncore()
53 return rc6_to_gt(rc)->i915; in rc6_to_i915()
64 struct intel_uncore *uncore = gt->uncore; in gen11_rc6_enable()
73 if (!intel_uc_uses_guc_rc(&gt->uc)) { in gen11_rc6_enable()
78 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in gen11_rc6_enable()
79 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in gen11_rc6_enable()
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/Linux-v6.1/drivers/nvme/host/
Dcore.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2011-2014, Intel Corporation.
8 #include <linux/blk-mq.h>
9 #include <linux/blk-integrity.h>
16 #include <linux/backing-dev.h>
27 #include <linux/nvme-auth.h>
64 "max power saving latency for new devices; use PM QOS to change per device");
83 "primary APST latency tolerance in us");
88 "secondary APST latency tolerance in us");
91 * nvme_wq - hosts nvme related works that are not reset or delete
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/Linux-v6.1/drivers/video/fbdev/riva/
Driva_hw.c3 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
10 |* Any use of this source code must include, in the user documenta- *|
14 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
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/Linux-v6.1/drivers/net/ethernet/intel/igb/
Digb_ptp.c1 // SPDX-License-Identifier: GPL-2.0+
14 /* The 82580 timesync updates the system timer every 8ns by 8ns,
38 * +--------------+ +---+---+------+
40 * +--------------+ +---+---+------+
43 * +----------+---+ +--------------+
45 * +----------+---+ +--------------+
50 * 2^45 * 10^-9 / 3600 = 9.77 hours.
53 * 2^40 * 10^-9 / 60 = 18.3 minutes.
67 #define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
78 struct e1000_hw *hw = &igb->hw; in igb_ptp_read_82576()
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/Linux-v6.1/include/linux/
Dsched.h1 /* SPDX-License-Identifier: GPL-2.0 */
34 #include <linux/posix-timers.h>
77 * We have two separate sets of flags: task->state
78 * is about runnability, while task->exit_state are
84 /* Used in tsk->state: */
90 /* Used in tsk->exit_state: */
94 /* Used in tsk->state again: */
107 #define TASK_ANY (TASK_STATE_MAX-1)
130 #define task_is_running(task) (READ_ONCE((task)->__state) == TASK_RUNNING)
132 #define task_is_traced(task) ((READ_ONCE(task->jobctl) & JOBCTL_TRACED) != 0)
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/Linux-v6.1/block/
Dblk-iolatency.c1 // SPDX-License-Identifier: GPL-2.0
3 * Block rq-qos base io controller
7 * - It's bio based, so the latency covers the whole block layer in addition to
9 * - We will throttle all IO that comes in here if we need to.
10 * - We use the mean latency over the 100ms window. This is because writes can
13 * - By default there's no throttling, we set the queue_depth to UINT_MAX so
17 * The hierarchy works like the cpu controller does, we track the latency at
19 * queue depth. This means that we only care about our latency targets at the
32 * an average latency of 5ms. If it does then we will throttle the "slow"
44 * number of IO's we're allowed to have in flight. This starts at (u64)-1 down
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Dbfq-iosched.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #include "blk-cgroup-rwstat.h"
30 * Soft real-time applications are extremely more latency sensitive
31 * than interactive ones. Over-raise the weight of the former to
39 * struct bfq_service_tree - per ioprio_class service tree.
41 * Each service tree represents a B-WF2Q+ scheduler on its own. Each
43 * bfq_service_tree. All the fields are protected by the queue lock
64 * struct bfq_sched_data - multi-class scheduler.
74 * queue requests are served according to B-WF2Q+.
79 * before the current in-service entity is expired, 2) the in-service
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Dblk-throttle.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "blk-cgroup-rwstat.h"
15 #include "blk-stat.h"
16 #include "blk-throttle.h"
31 #define DFL_LATENCY_TARGET (-1L)
36 * For HD, very small latency comes from sequential IO. Such IO is helpless to
46 /* We measure latency for request size from <= 4k to >= 1M */
50 unsigned long total_latency; /* ns / 1024 */
55 unsigned long latency; /* ns / 1024 */ member
94 return pd_to_blkg(&tg->pd); in tg_to_blkg()
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/Linux-v6.1/drivers/net/ethernet/8390/
Dlib8390.c3 Written 1992-94 by Donald Becker.
17 This is the chip-specific code for many 8390-based ethernet adaptors.
18 This is not a complete driver, it must be combined with board-specific
24 you have found something that needs changing. -- PG
29 Paul Gortmaker : remove set_bit lock, other cleanups.
34 Paul Gortmaker : rewrite Rx overrun handling as per NS specs.
40 Paul Gortmaker : add kmod support for auto-loading of the 8390
80 /* These are the operational function interfaces to board-specific
89 "page" value uses the 8390's 256-byte pages.
98 #define ei_reset_8390 (ei_local->reset_8390)
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/Linux-v6.1/drivers/cpufreq/
Dpowernow-k8.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * (c) 2003-2006 Advanced Micro Devices, Inc.
9 u32 numps; /* number of p-states */
10 u32 batps; /* number of p-states supported on battery */
13 * vid/fid pairings, but are modified during the ->target() call
19 u32 plllock; /* pll lock time, units 1 us */
36 * handle hotplug events - so just point at cpufreq pol->cpus
53 /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */
54 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
55 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
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/Linux-v6.1/tools/perf/pmu-events/arch/x86/icelakex/
Dicx-metrics.json4 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
11 …on": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
12 …"MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / SLO…
15 … latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branc…
39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS…
71 …i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding hea…
87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
92 "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
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/Linux-v6.1/drivers/base/power/
Ddomain.c1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/base/power/domain.c - Common code related to device power domains.
35 __routine = genpd->dev_ops.callback; \
46 void (*lock)(struct generic_pm_domain *genpd); member
54 mutex_lock(&genpd->mlock); in genpd_lock_mtx()
60 mutex_lock_nested(&genpd->mlock, depth); in genpd_lock_nested_mtx()
65 return mutex_lock_interruptible(&genpd->mlock); in genpd_lock_interruptible_mtx()
70 return mutex_unlock(&genpd->mlock); in genpd_unlock_mtx()
74 .lock = genpd_lock_mtx,
81 __acquires(&genpd->slock) in genpd_lock_spin()
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/Linux-v6.1/tools/perf/pmu-events/arch/x86/haswellx/
Dhsx-metrics.json7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
11 …on": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
15 … latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branc…
38 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
46 …i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding hea…
62 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
67 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
75 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
78 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
83 "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
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/Linux-v6.1/drivers/usb/core/
Dhub.c1 // SPDX-License-Identifier: GPL-2.0
50 #define USB_TP_TRANSMISSION_DELAY 40 /* ns */
51 #define USB_TP_TRANSMISSION_DELAY_MAX 65535 /* ns */
52 #define USB_PING_RESPONSE_TIME 400 /* ns */
54 /* Protect struct usb_device->state and ->children members
55 * Note: Both are also protected by ->dev.sem, except that ->state can
63 /* synchronize hub-port add/remove and peering operations */
73 * 10 seconds to send reply for the initial 64-byte descriptor request.
75 /* define initial 64-byte descriptor request timeout in milliseconds */
79 "initial 64-byte descriptor request timeout in milliseconds "
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/Linux-v6.1/tools/perf/pmu-events/arch/x86/broadwellx/
Dbdx-metrics.json7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
11 …on": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
15 … latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branc…
38 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
57 "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers",
68 …i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding hea…
84 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
89 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
97 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
100 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
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/Linux-v6.1/tools/perf/pmu-events/arch/x86/sapphirerapids/
Dspr-metrics.json4 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
11 …on": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
12 …etricExpr": "(topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
15 … latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branc…
39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
52 …"MetricExpr": "(1 - (tma_branch_mispredicts / tma_bad_speculation)) * INT_MISC.CLEAR_RESTEER_CYCLE…
71 …i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding hea…
87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
92 "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
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/Linux-v6.1/fs/proc/
Dbase.c1 // SPDX-License-Identifier: GPL-2.0
9 * 1999, Al Viro. Rewritten. Now it covers the whole per-process part.
11 * we allocate and fill in-core inodes upon lookup. They don't even
18 * 17-Jan-2005
25 * Embedded Linux Lab - 10LE Instituto Nokia de Tecnologia - INdT
35 * 21-Feb-2005
36 * Embedded Linux Lab - 10LE Instituto Nokia de Tecnologia - INdT
40 * 10-Mar-2005
41 * 10LE Instituto Nokia de Tecnologia - INdT:
62 #include <linux/generic-radix-tree.h>
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/Linux-v6.1/drivers/net/ethernet/intel/igc/
Digc_ptp.c1 // SPDX-License-Identifier: GPL-2.0
26 struct igc_hw *hw = &adapter->hw; in igc_ptp_read()
33 ts->tv_sec = sec; in igc_ptp_read()
34 ts->tv_nsec = nsec; in igc_ptp_read()
40 struct igc_hw *hw = &adapter->hw; in igc_ptp_write_i225()
42 wr32(IGC_SYSTIML, ts->tv_nsec); in igc_ptp_write_i225()
43 wr32(IGC_SYSTIMH, ts->tv_sec); in igc_ptp_write_i225()
50 struct igc_hw *hw = &igc->hw; in igc_ptp_adjfine_i225()
57 scaled_ppm = -scaled_ppm; in igc_ptp_adjfine_i225()
79 spin_lock_irqsave(&igc->tmreg_lock, flags); in igc_ptp_adjtime_i225()
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/Linux-v6.1/kernel/sched/
Dfair.c1 // SPDX-License-Identifier: GPL-2.0
43 #include <linux/memory-tiers.h>
60 * Targeted preemption latency for CPU-bound tasks:
62 * NOTE: this latency value is not the same as the concept of
63 * 'timeslice length' - timeslices in CFS are of variable length
64 * and have no persistent notion like in traditional, time-slice
68 * run vmstat and monitor the context-switches (cs) field)
76 * The initial- and re-scaling of tunables is configurable
80 * SCHED_TUNABLESCALING_NONE - unscaled, always *1
81 * SCHED_TUNABLESCALING_LOG - scaled logarithmical, *1+ilog(ncpus)
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/Linux-v6.1/drivers/md/
Ddm-ps-historical-service-time.c1 // SPDX-License-Identifier: GPL-2.0
5 * Keeps a time-weighted exponential moving average of the historical
20 * ns, and the weighting is pre-calculated.
25 #include "dm-path-selector.h"
32 #define DM_MSG_PREFIX "multipath historical-service-time"
48 spinlock_t lock; member
59 spinlock_t lock; member
70 * fixed_power - compute: x^n, in O(log n) time
94 result += 1UL << (frac_bits - 1); in fixed_power()
101 x += 1UL << (frac_bits - 1); in fixed_power()
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/Linux-v6.1/tools/perf/pmu-events/arch/x86/cascadelakex/
Dclx-metrics.json7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
11 …on": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
15 … latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branc…
39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS…
71 …i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding hea…
87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
92 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
100 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
103 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
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/Linux-v6.1/tools/perf/pmu-events/arch/x86/skylakex/
Dskx-metrics.json7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
11 …on": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
15 … latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branc…
39 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
52 …"MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS…
71 …i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding hea…
87 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
92 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
100 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
103 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
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/Linux-v6.1/include/uapi/linux/
Dhdreg.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
17 #define IDE_DRIVE_TASK_INVALID -1
137 * 0x01->0x02 Reserved
141 * 0x04->0x07 Reserved
146 * 0x09->0x0F Reserved
151 * 0x10->0x1F Reserved
153 #define WIN_READ 0x20 /* 28-Bit */
154 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
155 #define WIN_READ_LONG 0x22 /* 28-Bit */
156 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
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