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/Linux-v6.1/arch/mips/boot/dts/loongson/
Dloongson64v_4core_virtio.dts1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/irq.h>
5 /dts-v1/;
7 compatible = "loongson,loongson64v-4core-virtio";
8 #address-cells = <2>;
9 #size-cells = <2>;
11 cpuintc: interrupt-controller {
12 #address-cells = <0>;
13 #interrupt-cells = <1>;
14 interrupt-controller;
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Dloongson64g-package.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/irq.h>
6 #address-cells = <2>;
7 #size-cells = <2>;
9 cpuintc: interrupt-controller {
10 #address-cells = <0>;
11 #interrupt-cells = <1>;
12 interrupt-controller;
13 compatible = "mti,cpu-interrupt-controller";
16 package0: bus@1fe00000 {
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Dloongson64c-package.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/irq.h>
6 #address-cells = <2>;
7 #size-cells = <2>;
9 cpuintc: interrupt-controller {
10 #address-cells = <0>;
11 #interrupt-cells = <1>;
12 interrupt-controller;
13 compatible = "mti,cpu-interrupt-controller";
16 package0: bus@1fe00000 {
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Dloongson64c_8core_rs780e.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64c-package.dtsi"
6 #include "rs780e-pch.dtsi"
9 compatible = "loongson,loongson64c-8core-rs780e";
13 htpic: interrupt-controller@1efdfb000080 {
14 compatible = "loongson,htpic-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
Dloongson64c_4core_rs780e.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64c-package.dtsi"
6 #include "rs780e-pch.dtsi"
9 compatible = "loongson,loongson64c-4core-rs780e";
13 htpic: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htpic-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
Dloongson64c_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64c-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64c-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
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Dloongson64g_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64g-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64g-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
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Dloongson64-2k1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
21 #clock-cells = <1>;
35 #clock-cells = <0>;
36 compatible = "fixed-clock";
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/Linux-v6.1/Documentation/devicetree/bindings/interrupt-controller/
Dloongson,liointc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson-3 family of chips and
14 Loongson-2K1000 chip, as the primary package interrupt controller which
18 - $ref: /schemas/interrupt-controller.yaml#
23 - loongson,liointc-1.0
24 - loongson,liointc-1.0a
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Dloongson,htvec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Loongson-3 HyperTransport Interrupt Vector Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson-3 family of chips for
18 const: loongson,htvec-1.0
21 maxItems: 1
24 minItems: 1
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Dloongson,htpic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Loongson-3 HyperTransport Interrupt Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 - $ref: /schemas/interrupt-controller.yaml#
16 This interrupt controller is found in the Loongson-3 family of chips to transmit
21 const: loongson,htpic-1.0
24 maxItems: 1
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/Linux-v6.1/Documentation/loongarch/
Dirq-chip-model.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
9 Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
10 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
22 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
23 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
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/Linux-v6.1/drivers/irqchip/
Dirq-loongson-liointc.c1 // SPDX-License-Identifier: GPL-2.0
67 struct irq_chip_generic *gc = handler->priv->gc; in liointc_chained_handle_irq()
73 pending = readl(handler->priv->core_isr[core]); in liointc_chained_handle_irq()
77 if (handler->priv->has_lpc_irq_errata && in liointc_chained_handle_irq()
78 (handler->parent_int_map & gc->mask_cache & in liointc_chained_handle_irq()
88 generic_handle_domain_irq(gc->domain, bit); in liointc_chained_handle_irq()
100 writel(readl(gc->reg_base + offset) | mask, in liointc_set_bit()
101 gc->reg_base + offset); in liointc_set_bit()
103 writel(readl(gc->reg_base + offset) & ~mask, in liointc_set_bit()
104 gc->reg_base + offset); in liointc_set_bit()
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/Linux-v6.1/Documentation/translations/zh_CN/loongarch/
Dirq-chip-model.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/loongarch/irq-chip-model.rst
13 中的中断控制器（即IRQ芯片）包括CPUINTC（CPU Core Interrupt Controller）、LIOINTC（
15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片组的主中
16 断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。
18 CPUINTC是一种CPU内部的每个核本地的中断控制器，LIOINTC/EIOINTC/HTVECINTC是CPU内部的
19 全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
26 在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，
27 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
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