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/Linux-v5.15/Documentation/devicetree/bindings/pinctrl/
Dintel,lgm-io.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rahul.tanwar@linux.intel.com>
18 const: intel,lgm-io
25 '-pins$':
30 $ref: pinmux-node.yaml#
37 bias-pull-up: true
38 bias-pull-down: true
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/Linux-v5.15/drivers/mtd/nand/raw/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 <http://www.linux-mtd.infradead.org/doc/nand.html>.
125 include NAND flash controllers with built-in hardware ECC
160 - PXA3xx processors (NFCv1)
161 - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2)
162 - 64-bit Aramda platforms (7k, 8k) (NFCv2)
196 tristate "Toshiba Mobile IO NAND controller"
199 Support for NAND flash connected to a Toshiba Mobile IO
208 originally designed for Set-Top Box but is used on various BCM7xxx,
249 Controller Module with built-in hardware ECC capabilities.
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/Linux-v5.15/drivers/pinctrl/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
35 bool "Axis ARTPEC-6 pin controller driver"
40 This is the driver for the Axis ARTPEC-6 pin controller. This driver
43 found in Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
52 functionality. This driver supports the pinmux, push-pull and
57 tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support"
123 tristate "TI DA850/OMAP-L138/AM18XX pullup/pulldown groups"
128 Driver for TI DA850/OMAP-L138/AM18XX pinconf. Used to control
197 corresponding interrupt-controller.
225 tristate "One-register-per-pin type device tree based pinctrl driver"
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Dpinctrl-equilibrium.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pinctrl/pinconf-generic.h>
18 #include "pinctrl-equilibrium.h"
20 #define PIN_NAME_FMT "io-%d"
31 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
32 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); in eqbr_gpio_disable_irq()
33 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
43 gc->direction_input(gc, offset); in eqbr_gpio_enable_irq()
44 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_enable_irq()
45 writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET); in eqbr_gpio_enable_irq()
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/Linux-v5.15/drivers/tty/serial/
Dlantiq.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/io.h>
150 spin_lock_irqsave(&ltq_port->lock, flags); in lqasc_start_tx()
152 spin_unlock_irqrestore(&ltq_port->lock, flags); in lqasc_start_tx()
159 __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); in lqasc_stop_rx()
165 struct tty_port *tport = &port->state->port; in lqasc_rx_chars()
168 fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) & in lqasc_rx_chars()
170 while (fifocnt--) { in lqasc_rx_chars()
172 ch = readb(port->membase + LTQ_ASC_RBUF); in lqasc_rx_chars()
173 rsr = (__raw_readl(port->membase + LTQ_ASC_STATE) in lqasc_rx_chars()
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/Linux-v5.15/drivers/spi/
Dspi-lantiq-ssc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
11 #include <linux/io.h>
141 #define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */
190 return __raw_readl(spi->regbase + reg); in lantiq_ssc_readl()
196 __raw_writel(val, spi->regbase + reg); in lantiq_ssc_writel()
202 u32 val = __raw_readl(spi->regbase + reg); in lantiq_ssc_maskl()
206 __raw_writel(val, spi->regbase + reg); in lantiq_ssc_maskl()
211 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; in tx_fifo_level()
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Dspi-cadence-quadspi.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
17 #include <linux/io.h>
29 #include <linux/spi/spi-mem.h>
32 #define CQSPI_NAME "cadence-qspi"
265 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_is_idle()
272 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); in cqspi_get_rd_sram_level()
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/Linux-v5.15/
DMAINTAINERS9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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