| /Linux-v5.15/Documentation/devicetree/bindings/clock/ |
| D | intel,cgu-lgm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/intel,cgu-lgm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rahul.tanwar@linux.intel.com>
13 Lightning Mountain(LGM) SoC's Clock Generation Unit(CGU) driver provides
17 Please refer to include/dt-bindings/clock/intel,lgm-clk.h header file, it
23 const: intel,cgu-lgm
28 '#clock-cells':
32 - compatible
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| /Linux-v5.15/Documentation/devicetree/bindings/leds/ |
| D | leds-lgm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/leds-lgm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Lightning Mountain (LGM) SoC LED Serial Shift Output (SSO) Controller driver
10 - Zhu, Yi Xin <Yixin.zhu@intel.com>
11 - Amireddy Mallikarjuna reddy <mallikarjunax.reddy@intel.com>
15 const: intel,lgm-ssoled
23 clock-names:
25 - const: sso
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| /Linux-v5.15/Documentation/devicetree/bindings/mmc/ |
| D | arasan,sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: "mmc-controller.yaml#"
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
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| /Linux-v5.15/drivers/clk/x86/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0-only
2 obj-$(CONFIG_PMC_ATOM) += clk-pmc-atom.o
3 obj-$(CONFIG_X86_AMD_PLATFORM_DEVICE) += clk-fch.o
4 clk-x86-lpss-y := clk-lpss-atom.o
5 obj-$(CONFIG_X86_INTEL_LPSS) += clk-x86-lpss.o
6 obj-$(CONFIG_CLK_LGM_CGU) += clk-cgu.o clk-cgu-pll.o clk-lgm.o
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| D | clk-lgm.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
10 #include <dt-bindings/clock/intel,lgm-clk.h>
11 #include "clk-cgu.h"
119 * It's more efficient to provide an explicit table due to non-linear
223 * (network on chip peripheral clk) as critical clocks because
425 struct device *dev = &pdev->dev; in lgm_cgu_probe()
426 struct device_node *np = dev->of_node; in lgm_cgu_probe()
432 return -ENOMEM; in lgm_cgu_probe()
434 ctx->clk_data.num = CLK_NR_CLKS; in lgm_cgu_probe()
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| /Linux-v5.15/drivers/pwm/ |
| D | pwm-intel-lgm.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * - The hardware supports fixed period & configures only 2-wire mode.
7 * - Supports normal polarity. Does not support changing polarity.
8 * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
10 * - When duty cycle is changed, PWM output may be a mix of previous setting
13 * - It is a dedicated PWM fan controller. There are no other consumers for
17 #include <linux/clk.h>
36 #define LGM_PWM_MAX_RPM (BIT(16) - 1)
38 #define LGM_PWM_MAX_DUTY_CYCLE (BIT(8) - 1)
58 struct regmap *regmap = pc->regmap; in lgm_pwm_enable()
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| /Linux-v5.15/drivers/leds/blink/ |
| D | leds-lgm-sso.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
23 #define SSO_DEV_NAME "lgm-sso"
55 #define DATA_CLK_EDGE 0 /* 0-rising, 1-falling */
63 * SW - Software has to update the SWU bit
64 * GPTC - General Purpose timer is used as clock source
65 * FPID - Divided FSC clock (FPID) is used as clock source
149 if (rate <= priv->freq[i]) in sso_get_blink_rate_idx()
153 return -1; in sso_get_blink_rate_idx()
179 return pin - LED_GRP1_PIN_MAX; in sso_led_pin_blink_off()
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| /Linux-v5.15/drivers/mtd/nand/raw/ |
| D | intel-nand-controller.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 #include <linux/clk.h>
7 #include <linux/dma-direction.h>
8 #include <linux/dma-mapping.h>
102 #define NAND_DATA_IFACE_CHECK_ONLY -1
124 struct clk *clk; member
140 return readl_poll_timeout(ctrl->ebu + EBU_WAIT, status, in ebu_nand_waitrdy()
148 u8 cs_num = ebu_host->cs_num; in ebu_nand_readb()
151 val = readb(ebu_host->cs[cs_num].chipaddr + HSNAND_CS_OFFS); in ebu_nand_readb()
159 u8 cs_num = ebu_host->cs_num; in ebu_nand_writeb()
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| /Linux-v5.15/drivers/dma/lgm/ |
| D | lgm-dma.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2016 - 2020 Intel Corporation.
9 #include <linux/clk.h>
10 #include <linux/dma-mapping.h>
23 #include "../virt-dma.h"
25 #define DRIVER_NAME "lgm-dma"
68 #define DMA_MAX_CLASS (SZ_32 - 1)
142 #define DMA_ORRC_MAX_CNT (SZ_32 - 1)
149 #define DMA_MAX_DESC_NUM (SZ_8K - 1)
150 #define DMA_CHAN_BOFF_MAX (SZ_256 - 1)
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| /Linux-v5.15/drivers/tty/serial/ |
| D | lantiq.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk.h>
113 struct clk *freqclk;
115 struct clk *clk; member
150 spin_lock_irqsave(<q_port->lock, flags); in lqasc_start_tx()
152 spin_unlock_irqrestore(<q_port->lock, flags); in lqasc_start_tx()
159 __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); in lqasc_stop_rx()
165 struct tty_port *tport = &port->state->port; in lqasc_rx_chars()
168 fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) & in lqasc_rx_chars()
170 while (fifocnt--) { in lqasc_rx_chars()
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| /Linux-v5.15/drivers/phy/intel/ |
| D | phy-intel-lgm-emmc.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk.h>
48 struct clk *emmcclk;
64 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()
67 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in intel_emmc_phy_power()
75 rate = clk_get_rate(priv->emmcclk); in intel_emmc_phy_power()
78 dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate); in intel_emmc_phy_power()
88 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()
91 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in intel_emmc_phy_power()
102 ret = regmap_read_poll_timeout(priv->syscfg, EMMC_PHYSTAT_REG, in intel_emmc_phy_power()
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| D | phy-intel-lgm-combo.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Combo-PHY driver
5 * Copyright (C) 2019-2020 Intel Corporation.
9 #include <linux/clk.h>
20 #include <dt-bindings/phy/phy.h>
37 #define COMBO_PHY_ID(x) ((x)->parent->id)
38 #define PHY_ID(x) ((x)->id)
88 struct clk *core_clk;
107 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_iphy_enable()
108 u32 mask = BIT(cbphy->phy_mode * 2 + iphy->id); in intel_cbphy_iphy_enable()
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| /Linux-v5.15/drivers/pci/controller/dwc/ |
| D | pcie-intel-gw.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
18 #include "pcie-designware.h"
20 #define PORT_AFR_N_FTS_GEN12_DFT (SZ_128 - 1)
70 struct clk *core_clk;
88 writel(val, lpp->app_base + ofs); in pcie_app_wr()
94 pcie_update_bits(lpp->app_base, ofs, mask, val); in pcie_app_wr_mask()
99 return dw_pcie_readl_dbi(&lpp->pci, ofs); in pcie_rc_cfg_rd()
104 dw_pcie_writel_dbi(&lpp->pci, ofs, val); in pcie_rc_cfg_wr()
110 pcie_update_bits(lpp->pci.dbi_base, ofs, mask, val); in pcie_rc_cfg_wr_mask()
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| /Linux-v5.15/drivers/mmc/host/ |
| D | sdhci-of-arasan.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-pltfm.h"
55 * On some SoCs the syscon area has a feature where the upper 16-bits of
56 * each 32-bit register act as a write mask for the lower 16-bits. This allows
64 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
68 * @shift: Bit offset within @reg of this field (or -1 if not avail)
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| /Linux-v5.15/drivers/spi/ |
| D | spi-lantiq-ssc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
10 #include <linux/clk.h>
141 #define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */
168 struct clk *spi_clk;
169 struct clk *fpi_clk;
190 return __raw_readl(spi->regbase + reg); in lantiq_ssc_readl()
196 __raw_writel(val, spi->regbase + reg); in lantiq_ssc_writel()
202 u32 val = __raw_readl(spi->regbase + reg); in lantiq_ssc_maskl()
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| D | spi-cadence-quadspi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
9 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
29 #include <linux/spi/spi-mem.h>
32 #define CQSPI_NAME "cadence-qspi"
62 struct clk *clk; member
265 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_is_idle()
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| /Linux-v5.15/ |
| D | MAINTAINERS | 9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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