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/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dmicrochip,lan966x-serdes.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/microchip,lan966x-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Lan966x Serdes controller
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 Lan966x has 7 interfaces, consisting of 2 copper transceivers(CU),
16 interfaces. The Serdes controller will allow to configure these interfaces
23 interface SerDes 2.
27 pattern: "^serdes@[0-9a-f]+$"
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/Linux-v6.1/Documentation/devicetree/bindings/net/
Dmicrochip,lan966x-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Lan966x Ethernet switch controller
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
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/Linux-v6.1/arch/arm/boot/dts/
Dlan966x-pcb8290.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x-pcb8290.dts - Device Tree file for LAN966X-PCB8290 board
9 /dts-v1/;
10 #include "lan966x.dtsi"
11 #include "dt-bindings/phy/phy-lan966x-serdes.h"
15 compatible = "microchip,lan9668-pcb8290", "microchip,lan9668", "microchip,lan966";
17 gpio-restart {
18 compatible = "gpio-restart";
29 miim_a_pins: mdio-pins {
35 pps_out_pins: pps-out-pins {
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Dlan966x-pcb8291.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x_pcb8291.dts - Device Tree file for PCB8291
5 /dts-v1/;
6 #include "lan966x.dtsi"
7 #include "dt-bindings/phy/phy-lan966x-serdes.h"
10 model = "Microchip EVB - LAN9662";
11 compatible = "microchip,lan9662-pcb8291", "microchip,lan9662", "microchip,lan966";
14 stdout-path = "serial0:115200n8";
21 gpio-restart {
22 compatible = "gpio-restart";
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Dlan966x-kontron-kswitch-d10-mmt.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "lan966x.dtsi"
8 #include "dt-bindings/phy/phy-lan966x-serdes.h"
16 stdout-path = "serial0:115200n8";
19 gpio-restart {
20 compatible = "gpio-restart";
27 atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
31 pinctrl-0 = <&usart0_pins>;
32 pinctrl-names = "default";
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Dlan966x-pcb8309.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x_pcb8309.dts - Device Tree file for PCB8309
5 /dts-v1/;
6 #include "lan966x.dtsi"
7 #include "dt-bindings/phy/phy-lan966x-serdes.h"
10 model = "Microchip EVB - LAN9662";
11 compatible = "microchip,lan9662-pcb8309", "microchip,lan9662", "microchip,lan966";
20 stdout-path = "serial0:115200n8";
23 gpio-restart {
24 compatible = "gpio-restart";
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Dlan966x-kontron-kswitch-d10-mmt-8g.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "lan966x-kontron-kswitch-d10-mmt.dtsi"
11 compatible = "kontron,kswitch-d10-mmt-8g", "kontron,s1921",
16 phy2: ethernet-phy@3 {
20 phy3: ethernet-phy@4 {
26 phys = <&serdes 2 SERDES6G(0)>;
27 phy-handle = <&phy2>;
28 phy-mode = "sgmii";
29 managed = "in-band-status";
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Dlan966x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mfd/atmel-flexcom.h>
14 #include <dt-bindings/dma/at91.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/clock/microchip,lan966x.h>
21 interrupt-parent = <&gic>;
22 #address-cells = <1>;
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Dlan966x-kontron-kswitch-d10-mmt-6g-2gs.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for the Kontron KSwitch D10 MMT 6G-2GS
6 /dts-v1/;
7 #include "lan966x-kontron-kswitch-d10-mmt.dtsi"
10 model = "Kontron KSwitch D10 MMT 6G-2GS";
11 compatible = "kontron,kswitch-d10-mmt-6g-2gs", "kontron,s1921",
21 i2c-bus = <&i2c4>;
22 los-gpios = <&sgpio_in 1 0 GPIO_ACTIVE_HIGH>;
23 mod-def0-gpios = <&sgpio_in 1 1 GPIO_ACTIVE_LOW>;
24 maximum-power-milliwatt = <2500>;
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/Linux-v6.1/drivers/net/ethernet/microchip/lan966x/
Dlan966x_main.c1 // SPDX-License-Identifier: GPL-2.0+
25 #define XTR_VALID_BYTES(x) (4 - (((x) >> 24) & 3))
30 { .compatible = "microchip,lan966x-switch" },
65 struct lan966x *lan966x) in lan966x_create_targets() argument
80 dev_err(&pdev->dev, "Invalid resource\n"); in lan966x_create_targets()
81 return -EINVAL; in lan966x_create_targets()
84 begin[idx] = devm_ioremap(&pdev->dev, in lan966x_create_targets()
85 iores[idx]->start, in lan966x_create_targets()
88 dev_err(&pdev->dev, "Unable to get registers: %s\n", in lan966x_create_targets()
89 iores[idx]->name); in lan966x_create_targets()
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Dlan966x_phylink.c1 // SPDX-License-Identifier: GPL-2.0+
15 struct lan966x_port *port = netdev_priv(to_net_dev(config->dev)); in lan966x_phylink_mac_select()
17 return &port->phylink_pcs; in lan966x_phylink_mac_select()
30 struct lan966x_port *port = netdev_priv(to_net_dev(config->dev)); in lan966x_phylink_mac_prepare()
34 if (port->serdes) { in lan966x_phylink_mac_prepare()
35 err = phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET, in lan966x_phylink_mac_prepare()
38 netdev_err(to_net_dev(config->dev), in lan966x_phylink_mac_prepare()
39 "Could not set mode of SerDes\n"); in lan966x_phylink_mac_prepare()
54 struct lan966x_port *port = netdev_priv(to_net_dev(config->dev)); in lan966x_phylink_mac_link_up()
55 struct lan966x_port_config *port_config = &port->config; in lan966x_phylink_mac_link_up()
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Dlan966x_main.h1 /* SPDX-License-Identifier: GPL-2.0+ */
46 #define PGID_CPU (PGID_AGGR - 6)
47 #define PGID_UC (PGID_AGGR - 5)
48 #define PGID_BC (PGID_AGGR - 4)
49 #define PGID_MC (PGID_AGGR - 3)
50 #define PGID_MCIPV4 (PGID_AGGR - 2)
51 #define PGID_MCIPV6 (PGID_AGGR - 1)
53 /* Non-reserved PGIDs, used for general purpose */
87 #define SE_IDX_QUEUE 0 /* 0-79 : Queue scheduler elements */
88 #define SE_IDX_PORT 80 /* 80-89 : Port schedular elements */
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/Linux-v6.1/drivers/phy/microchip/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
7 tristate "Microchip Sparx5 SerDes PHY driver"
13 Enable this for support of the 10G/25G SerDes on Microchip Sparx5.
16 tristate "SerDes PHY driver for Microchip LAN966X"
21 Enable this for supporting SerDes muxing with Microchip LAN966X
Dlan966x_serdes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/phy/phy-lan966x-serdes.h>
186 /* Note: SerDes HSIO is configured in 1G_LAN mode */ in lan966x_sd6g40_reg_cfg()
187 lan_rmw(HSIO_SD_CFG_LANE_10BIT_SEL_SET(res_struct->lane_10bit_sel) | in lan966x_sd6g40_reg_cfg()
188 HSIO_SD_CFG_RX_RATE_SET(res_struct->rx_rate) | in lan966x_sd6g40_reg_cfg()
189 HSIO_SD_CFG_TX_RATE_SET(res_struct->tx_rate) | in lan966x_sd6g40_reg_cfg()
190 HSIO_SD_CFG_TX_INVERT_SET(res_struct->tx_invert) | in lan966x_sd6g40_reg_cfg()
191 HSIO_SD_CFG_RX_INVERT_SET(res_struct->rx_invert) | in lan966x_sd6g40_reg_cfg()
192 HSIO_SD_CFG_LANE_LOOPBK_EN_SET(res_struct->lane_loopbk_en) | in lan966x_sd6g40_reg_cfg()
203 macro->ctrl->regs, HSIO_SD_CFG(idx)); in lan966x_sd6g40_reg_cfg()
[all …]
/Linux-v6.1/
DMAINTAINERS9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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