Home
last modified time | relevance | path

Searched full:l3 (Results 1 – 25 of 578) sorted by relevance

12345678910>>...24

/Linux-v5.10/drivers/bus/
Domap_l3_noc.c2 * OMAP L3 Interconnect error handling driver
31 * @l3: pointer to l3 struct
43 * 1) Custom errors in L3 :
45 * 2) Standard L3 error:
47 * L3 tries to access target while it is idle
58 static int l3_handle_target(struct omap_l3 *l3, void __iomem *base, in l3_handle_target() argument
122 l3->mst_addr_mask) >> __ffs(l3->mst_addr_mask); in l3_handle_target()
124 for (k = 0, master = l3->l3_masters; k < l3->num_masters; in l3_handle_target()
142 "%s:L3 %s Error: MASTER %s TARGET %s (%s)%s%s\n", in l3_handle_target()
143 dev_name(l3->dev), in l3_handle_target()
[all …]
Domap_l3_smx.c3 * OMAP3XXX L3 Interconnect Driver
130 * @l3: struct omap3_l3 *
140 static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3, in omap3_l3_block_irq() argument
159 struct omap3_l3 *l3 = _l3; in omap3_l3_app_irq() local
168 int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR; in omap3_l3_app_irq()
170 status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0); in omap3_l3_app_irq()
179 status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1); in omap3_l3_app_irq()
186 base = l3->rt + omap3_l3_bases[int_type][err_source]; in omap3_l3_app_irq()
190 ret |= omap3_l3_block_irq(l3, error, error_addr); in omap3_l3_app_irq()
207 .compatible = "ti,omap3-l3-smx",
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/haswell/
Duncore.json31 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor c…
32 …"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor …
67 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line i…
68 …"PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line …
103 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in so…
104 …"PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in s…
115 "BriefDescription": "L3 Lookup read request that access cache and found line in M-state.",
116 "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",
127 "BriefDescription": "L3 Lookup write request that access cache and found line in M-state.",
128 "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
[all …]
Dmemory.json404 "PublicDescription": "Counts all requests miss in the L3",
412 "BriefDescription": "Counts all requests miss in the L3",
417 "PublicDescription": "miss the L3 and the data is returned from local dram",
425 "BriefDescription": "miss the L3 and the data is returned from local dram",
430 "PublicDescription": "miss in the L3",
438 "BriefDescription": "miss in the L3",
443 …"PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned…
451 …"BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned …
456 "PublicDescription": "Counts all demand & prefetch code reads miss in the L3",
464 "BriefDescription": "Counts all demand & prefetch code reads miss in the L3",
[all …]
Dcache.json186 "BriefDescription": "Core-originated cacheable demand requests missed L3",
196 "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
532 …event counts retired load uops in which data sources were data hits in the L3 cache without snoops…
539 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
576 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
600 …"BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed …
606 …"PublicDescription": "This event counts retired load uops that hit in the L3 cache, but required a…
613 …"BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-…
619 …"PublicDescription": "This event counts retired load uops that hit in the L3 cache, but required a…
626 … "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
[all …]
/Linux-v5.10/arch/sparc/kernel/
Dhead_64.S175 mov 1, %l3
176 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
177 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
199 mov 4, %l3
200 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
201 mov 1, %l3
202 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
206 mov 64, %l3
207 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
214 mov (1b - prom_boot_mapped_pc), %l3
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/powerpc/power8/
Dcache.json5 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node …
6 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node …
11 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node …
12 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node …
65 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand …
66 …"PublicDescription": "The processor's data cache was reloaded from local core's L3 due to either o…
71 "BriefDescription": "Demand LD - L3 Miss (not L2 hit and not L3 hit)",
77 …ssor's data cache was reloaded from a location other than the local core's L3 due to a demand load…
78 …ssor's data cache was reloaded from a location other than the local core's L3 due to either only d…
83 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch co…
[all …]
Dmetrics.json207 …escription": "Cycles stalled by GCT empty due to Icache misses that resolve in the local L2 or L3",
255 …"BriefDescription": "Cycles stalled by D-Cache Misses that resolved in the local L2 or L3, where t…
261 "BriefDescription": "Cycles stalled by D-Cache Misses that resolved in the local L2 or L3",
267 …"BriefDescription": "Cycles stalled by D-Cache Misses that resolved in the local L2 or L3, where t…
456 "BriefDescription": "% of DL1 Reloads from Distant L2 or L3 (Modified) per Inst",
462 "BriefDescription": "% of DL1 Reloads from Distant L2 or L3 (Shared) per Inst",
522 "BriefDescription": "% of DL1 reloads from Private L3 M state, other core per Inst",
528 "BriefDescription": "% of DL1 reloads from Private L3 S tate, other core per Inst",
534 …"BriefDescription": "Percentage of L3 load hits per instruction where the load collided with a pen…
540 "BriefDescription": "% of DL1 reloads from L3 per Inst",
[all …]
Dfrontend.json89 …uction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node …
90 …uction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node …
95 …truction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node …
96 …truction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node …
149 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an…
150 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 due to e…
156 "PublicDescription": "Inst from L3 miss"
161 …Instruction cache was reloaded from a location other than the local core's L3 due to a instruction…
162 …Instruction cache was reloaded from a location other than the local core's L3 due to either an ins…
167 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 with disp…
[all …]
Dmarked.json35 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node …
41 …ation in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node …
47 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node …
53 …uration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node …
155 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a marked …
161 …ssor's data cache was reloaded from a location other than the local core's L3 due to a marked load…
167 … "Duration in cycles to reload from a location other than the local core's L3 due to a marked load…
173 "BriefDescription": "Duration in cycles to reload from local core's L3 due to a marked load",
179 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch co…
185 …"BriefDescription": "Duration in cycles to reload from local core's L3 with dispatch conflict due …
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/interconnect/
Dqcom,osm-l3.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
7 title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
13 L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
14 The OSM L3 interconnect provider aggregates the L3 bandwidth requests
20 - qcom,sc7180-osm-l3
21 - qcom,sdm845-osm-l3
22 - qcom,sm8150-osm-l3
23 - qcom,sm8250-epss-l3
57 compatible = "qcom,sdm845-osm-l3";
/Linux-v5.10/tools/perf/pmu-events/arch/x86/haswellx/
Dmemory.json407 "BriefDescription": "Counts demand data reads miss in the L3",
412 "PublicDescription": "Counts demand data reads miss in the L3",
420 …"BriefDescription": "Counts demand data reads miss the L3 and the data is returned from local dram…
425 …"PublicDescription": "Counts demand data reads miss the L3 and the data is returned from local dra…
433 "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3",
438 "PublicDescription": "Counts all demand data writes (RFOs) miss in the L3",
446 …"BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned fro…
451 …"PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned fr…
459 …"BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is tra…
464 …"PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is tr…
[all …]
Dcache.json182 "BriefDescription": "Core-originated cacheable demand requests missed L3",
192 "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
530 …"BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops requ…
536 "PublicDescription": "Retired load uops with L3 cache hits as data sources.",
569 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
575 "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .",
594 …"BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed …
606 …"BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-…
618 … "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
630 …"BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.…
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/skylake/
Duncore.json19 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor c…
20 …"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor …
55 "BriefDescription": "L3 Lookup write request that access cache and found line in M-state",
56 "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
67 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
68 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
79 "BriefDescription": "L3 Lookup read request that access cache and found line in I-state",
80 "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
91 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
92 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/broadwell/
Duncore.json19 …"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor c…
20 …"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor …
55 "BriefDescription": "L3 Lookup read request that access cache and found line in M-state",
56 "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",
67 "BriefDescription": "L3 Lookup write request that access cache and found line in M-state",
68 "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
79 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
80 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
91 "BriefDescription": "L3 Lookup read request that access cache and found line in I-state",
92 "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/arm/omap/
Dl3-noc.txt1 * TI - L3 Network On Chip (NoC)
7 - compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
8 Should be "ti,omap4-l3-noc" for OMAP4 family
9 Should be "ti,omap5-l3-noc" for OMAP5 family
10 Should be "ti,dra7-l3-noc" for DRA7 family
11 Should be "ti,am4372-l3-noc" for AM43 family
12 - reg: Contains L3 register address range for each noc domain.
18 compatible = "ti,omap4-l3-noc", "simple-bus";
/Linux-v5.10/arch/arm/mach-omap2/
Domap_hwmod_33xx_43xx_interconnect_data.c21 /* mpu -> l3 main */
29 /* l3 main -> l3 s */
37 /* l3 s -> l4 per/ls */
45 /* l3 s -> l4 wkup */
53 /* l3 main -> l3 instr */
69 /* l3 s -> l3 main*/
85 /* l3 main -> ocmc */
/Linux-v5.10/tools/perf/pmu-events/arch/powerpc/power9/
Dother.json35 "BriefDescription": "L3 initiated LCO received retry on port 2 (can try 4 times)"
45 …ssor's data cache was reloaded from a location other than the local core's L3 due to a marked load"
50 …try was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due…
120 …"BriefDescription": "L3 TM CAM is full when a L2 castout of TM_SC line occurs. Line is pushed to …
160 "BriefDescription": "L3 PF from Off chip memory"
190 …"BriefDescription": "TM snoop that is a store hits line in L3 in T, Tn or Te state (shared modifie…
205 …uration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due…
235 … "BriefDescription": "Core TM load hits line in L3 in TM_SC state and causes it to be invalidated"
245 "BriefDescription": "L3 PF sent with nodal scope port 1, counts even retried requests"
260 "BriefDescription": "L3 CO received retry port 3 (memory only), every retry counted"
[all …]
Dmarked.json10 …ory Entry was reloaded to a level 1 page walk cache from beyond the core's L3 data cache. The sour…
20 …ble Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due…
50 …Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This imp…
70 …Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due…
85 …Instruction cache was reloaded from a location other than the local core's L3 due to a instruction…
95 …try was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due…
100 …Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due…
110 … "Duration in cycles to reload from a location other than the local core's L3 due to a marked load"
180 …ocessor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due…
185 …essor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due…
[all …]
Dmetrics.json80 …iefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)",
86 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a confl…
92 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 without conf…
98 "BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3",
104 "BriefDescription": "Completion stall due to cache miss resolving missed the L3",
271 …n Completion Table empty for this thread due to icache misses that were sourced from the local L3",
277 …r this thread due to icache misses that were sourced from beyond the local L3. The source could be…
601 "BriefDescription": "% of DL1 Reloads from Distant L2 or L3 (Modified) per Inst",
607 "BriefDescription": "% of DL1 Reloads from Distant L2 or L3 (Shared) per Inst",
643 "BriefDescription": "% of DL1 reloads from Private L3 M state, other core per Inst",
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/broadwellx/
Dmemory.json436 "BriefDescription": "Counts all requests miss in the L3",
441 "PublicDescription": "Counts all requests miss in the L3",
449 …"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or s…
454 …"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or …
462 …"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modifi…
467 …"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modif…
475 …"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data i…
480 …"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data …
488 …"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data i…
493 …"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data …
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/x86/skylakex/
Dmemory.json3 …"BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned f…
16 "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3.",
29 …"BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the su…
39 …"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the dat…
52 … "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3.",
65 …"BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data i…
87 …"BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from…
110 …"BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from r…
133 "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3.",
146 …"BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or …
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/edac/
Dapm-xgene-edac.txt8 L3 - L3 cache controller
24 - interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error
39 Required properties for L3 subnode:
40 - compatible : Shall be "apm,xgene-edac-l3" or
41 "apm,xgene-edac-l3-v2".
42 - reg : First resource shall be the L3 EDAC resource.
46 "apm,xgene-edac-l3-soc" for general value reporting
104 compatible = "apm,xgene-edac-l3";
/Linux-v5.10/drivers/gpu/drm/i915/gt/
Dintel_mocs.c80 /* L3 caching options */
137 * - used by the L3 for all of its evictions.
140 * - used to force L3 uncachable cycles.
141 * Thus it is expected to make the surface L3 uncacheable.
158 /* Base - L3 + LLC */ \
166 /* Base - L3 */ \
178 /* Age 0 - L3 + LLC */ \
186 /* Age: Don't Chg. - L3 + LLC */ \
194 /* No AOM - L3 + LLC */ \
202 /* No AOM; Age 0 - L3 + LLC */ \
[all …]
/Linux-v5.10/tools/perf/pmu-events/arch/s390/cf_z13/
Dextended.json111 "BriefDescription": "L1D On-Chip L3 Sourced Writes",
118 "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
132 "BriefDescription": "L1D On-Node L3 Sourced Writes with Intervention",
139 "BriefDescription": "L1D On-Node L3 Sourced Writes",
153 "BriefDescription": "L1D On-Drawer L3 Sourced Writes with Intervention",
160 "BriefDescription": "L1D On-Drawer L3 Sourced Writes",
174 "BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes with Intervention",
181 "BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes",
188 "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes",
195 "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes with Intervention",
[all …]

12345678910>>...24