Lines Matching full:l3
35 "BriefDescription": "L3 initiated LCO received retry on port 2 (can try 4 times)"
45 …ssor's data cache was reloaded from a location other than the local core's L3 due to a marked load"
50 …try was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due…
120 …"BriefDescription": "L3 TM CAM is full when a L2 castout of TM_SC line occurs. Line is pushed to …
160 "BriefDescription": "L3 PF from Off chip memory"
190 …"BriefDescription": "TM snoop that is a store hits line in L3 in T, Tn or Te state (shared modifie…
205 …uration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due…
235 … "BriefDescription": "Core TM load hits line in L3 in TM_SC state and causes it to be invalidated"
245 "BriefDescription": "L3 PF sent with nodal scope port 1, counts even retried requests"
260 "BriefDescription": "L3 CO received retry port 3 (memory only), every retry counted"
265 … "BriefDescription": "Any port snooper hit L3. Up to 4 can happen in a cycle but we only count 1"
270 "BriefDescription": "L3 CO to memory port 0 with or without data"
310 "BriefDescription": "L3 Hits for demand LDs"
330 "BriefDescription": "L3 Hits (L2 miss hitting L3, including data/instrn/xlate)"
340 "BriefDescription": "L3 initiated LCO received retry on port 1 (can try 4 times)"
350 …"BriefDescription": "Duration in cycles to reload from local core's L3 without dispatch conflicts …
375 "BriefDescription": "Completion stall due to cache miss resolving missed the L3"
385 … in cycles to reload either shared or modified data from another core's L2/L3 on a different chip …
405 …"BriefDescription": "TM snoop that is a store hits line in L3 in M or Mu state (exclusive modified…
435 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch co…
445 "BriefDescription": "Marked L3 misses that can throw a synchronous interrupt"
485 "BriefDescription": "L3 CO received retry port 2 (memory only), every retry counted"
560 "BriefDescription": "L3 PF missed in L3"
565 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or …
570 "BriefDescription": "L3 PF sent with grp scope port 1, counts even retried requests"
630 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch co…
635 "BriefDescription": "Dataless L3 LCO sent port 1"
675 "BriefDescription": "L3 CO to memory port 1 with or without data"
685 …"BriefDescription": "L3 load prefetch, sourced from a hardware or software stream, was sent to the…
745 "BriefDescription": "L3 initiated LCO received retry on port 3 (can try 4 times)"
760 "BriefDescription": "L3 PF from Off chip cache"
790 "BriefDescription": "L3 castins miss (total count)"
805 "BriefDescription": "L3 PF from On chip cache"
830 …"BriefDescription": "L3 load prefetch, sourced from a software prefetch stream, was sent to the ne…
840 …r's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due…
850 "BriefDescription": "L3 PF from On chip memory"
910 …"BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's L3 on t…
920 … "BriefDescription": "TM snoop hits line in L3 that is TM_SC state and causes it to be invalidated"
925 "BriefDescription": "L3 Transient prefetch received from L2"
970 "BriefDescription": "L3 PF sent with sys scope port 0, counts even retried requests"
1005 …cription": "L3 CO of line in Mep state (includes casthrough to memory). The Mepf state indicates …
1010 "BriefDescription": "L3 Lateral Castins Hit"
1015 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node …
1055 … loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip …
1075 …"BriefDescription": "L3 CO to memory OR of port 0 and 1 (lossy = may undercount if two cresp come …
1095 …"BriefDescription": "Non-TM snoop hits line in L3 that is TM_SC state and causes it to be invalida…
1130 "BriefDescription": "L3 Misses for demand LDs"
1155 …ble Entry was reloaded to a level 4 page walk cache from beyond the core's L3 data cache. This is …
1195 …"BriefDescription": "Duration in cycles to reload from local core's L3 with dispatch conflict due …
1200 "BriefDescription": "Duration in cycles to reload from local core's L3 due to a marked load"
1205 …"BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's L3 on…
1210 …n cache was reloaded either shared or modified data from another core's L2/L3 on a different chip …
1245 "BriefDescription": "L3 initiated LCO received retry on port 0 (can try 4 times)"
1330 "BriefDescription": "L3 CO received retry port 1 (memory only), every retry counted"
1335 "BriefDescription": "L3 Castins Hit (total count)"
1450 "BriefDescription": "L3 CO to L3.1 (LCO) port 1 with or without data"
1485 …truction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due…
1495 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict…
1570 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch…
1580 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch…
1585 "BriefDescription": "L3 PF sent with nodal scope port 0, counts even retried requests"
1615 …ble Entry was reloaded to a level 2 page walk cache from beyond the core's L3 data cache. This imp…
1660 "BriefDescription": "L3 PF received retry port 3, every retry counted"
1730 "BriefDescription": "L3 PF received retry port 0, every retry counted"
1745 "BriefDescription": "L3 PF received retry port 2, every retry counted"
1755 …leanifdirty CO to the L3 (ie created an SC line in the L3) OR L2 TM_store hit dirty HPC line and L…
1815 …try was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node …
1820 "BriefDescription": "L3 PF hit in L3 (abandoned)"
1875 …"BriefDescription": "L3 CO to L3.1 OR of port 0 and 1 (lossy = may undercount if two cresps come i…
1900 …ation in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node …
1915 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node …
1945 …"BriefDescription": "Duration in cycles to reload from local core's L3 without conflict due to a m…
2005 "BriefDescription": "L3 PF sent with sys scope port 1, counts even retried requests"
2010 …ble Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due…
2045 "BriefDescription": "L3 PF sent with grp scope port 0, counts even retried requests"
2055 …a cache was reloaded either shared or modified data from another core's L2/L3 on a different chip …
2060 … loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due…
2085 …"BriefDescription": "L3 castout of line that was StoreCopy (original value of speculatively writte…
2105 "BriefDescription": "L3 Misses (L2 miss also missing L3, including data/instrn/xlate)"
2135 …"BriefDescription": "Any port snooper L3 miss or collision. Up to 4 can happen in a cycle but we …
2165 "BriefDescription": "L3 CO received retry port 0 (memory only), every retry counted"
2175 "BriefDescription": "L3 Lateral Castins Miss"
2185 "BriefDescription": "L3 CO to L3.1 (LCO) port 0 with or without data"
2195 "BriefDescription": "L3 PF received retry port 1, every retry counted"
2220 …essor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due…
2225 … "BriefDescription": "Total L3 COs occurred on LCO L3.1 (good cresp, may end up in mem on a retry)"
2235 "BriefDescription": "RD machine hit L3 PF machine"
2255 "BriefDescription": "Dataless L3 LCO sent port 0"
2300 … "BriefDescription": "L3 castout occurring (does not include casthrough or log writes (cinj/dmaw))"
2305 "BriefDescription": "L3 castin of cache inject"