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/Linux-v5.10/Documentation/devicetree/bindings/arm/msm/
Dqcom,kpss-acc.txt1 Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
3 The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
4 There is one ACC register region per CPU within the KPSS remapped region as
5 well as an alias register region that remaps accesses to the ACC associated
10 - compatible:
14 "qcom,kpss-acc-v1"
15 "qcom,kpss-acc-v2"
17 - reg:
19 Value type: <prop-encoded-array>
24 - clocks:
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/Linux-v5.10/arch/arm/boot/dts/
Dqcom-msm8960.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/mfd/qcom-rpm.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&intc>;
17 #address-cells = <1>;
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Dqcom-ipq4019.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
18 interrupt-parent = <&intc>;
20 reserved-memory {
21 #address-cells = <0x1>;
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Dqcom-apq8084.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
6 #include <dt-bindings/gpio/gpio.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
13 interrupt-parent = <&intc>;
15 reserved-memory {
16 #address-cells = <1>;
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Dqcom-ipq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
6 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <1>;
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Dqcom-apq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <1>;
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Dqcom-msm8974.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
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/Linux-v5.10/Documentation/devicetree/bindings/arm/
Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
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/Linux-v5.10/drivers/clk/qcom/
Dkpss-xcc.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk-provider.h>
26 { .compatible = "qcom,kpss-acc-v1", .data = (void *)1UL },
27 { .compatible = "qcom,kpss-gcc" },
40 id = of_match_device(kpss_xcc_match_table, &pdev->dev); in kpss_xcc_driver_probe()
42 return -ENODEV; in kpss_xcc_driver_probe()
45 base = devm_ioremap_resource(&pdev->dev, res); in kpss_xcc_driver_probe()
49 if (id->data) { in kpss_xcc_driver_probe()
50 if (of_property_read_string_index(pdev->dev.of_node, in kpss_xcc_driver_probe()
51 "clock-output-names", in kpss_xcc_driver_probe()
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/Linux-v5.10/arch/arm/mach-qcom/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
58 node = of_find_compatible_node(NULL, NULL, "qcom,gcc-msm8660"); in scss_release_secondary()
61 return -ENXIO; in scss_release_secondary()
67 return -ENOMEM; in scss_release_secondary()
87 return -ENODEV; in kpssv1_release_secondary()
89 acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0); in kpssv1_release_secondary()
91 ret = -ENODEV; in kpssv1_release_secondary()
97 ret = -ENODEV; in kpssv1_release_secondary()
103 ret = -ENOMEM; in kpssv1_release_secondary()
109 ret = -ENOMEM; in kpssv1_release_secondary()
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/Linux-v5.10/arch/arm64/boot/dts/qcom/
Dqcs404.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
6 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/thermal/thermal.h>
12 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
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