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/Linux-v6.1/Documentation/devicetree/bindings/i2c/
Dopencores,i2c-ocores.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Korsgaard <peter@korsgaard.com>
11 - Andrew Lunn <andrew@lunn.ch>
14 - $ref: /schemas/i2c/i2c-controller.yaml#
19 - items:
20 - enum:
21 - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC
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Dmicrochip,corei2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - items:
19 - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
20 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
21 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
32 clock-frequency:
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Di2c-demux-pinctrl.txt1 Pinctrl-based I2C Bus DeMux
5 the pinctrl device tree bindings. This may be used to select one I2C IP core at
7 IP core on the SoC. The most simple example is to fall back to GPIO bitbanging
8 if your current runtime configuration hits an errata of the internal IP core.
10 +-------------------------------+
12 | | +-----+ +-----+
13 | +------------+ | | dev | | dev |
14 | |I2C IP Core1|--\ | +-----+ +-----+
15 | +------------+ \-------+ | | |
16 | |Pinctrl|--|------+--------+
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/Linux-v6.1/Documentation/devicetree/bindings/media/
Dnxp,imx-mipi-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <rmfrfs@gmail.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 description: |-
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
15 receiver IP core named CSIS. The IP core originates from Samsung, and may be
[all …]
Dsamsung-fimc.txt2 ----------------------------------------------
4 The S5P/Exynos SoC Camera subsystem comprises of multiple sub-devices
6 the S5P SoCs series known as CAMIF), MIPI CSIS, FIMC-LITE and FIMC-IS (ISP).
8 The sub-subdevices are defined as child nodes of the common 'camera' node which
10 any single sub-device, like common camera port pins or the CAMCLK clock outputs
14 --------------------
18 - compatible: must be "samsung,fimc", "simple-bus"
19 - clocks: list of clock specifiers, corresponding to entries in
20 the clock-names property;
21 - clock-names : must contain "sclk_cam0", "sclk_cam1", "pxl_async0",
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Dsamsung-mipi-csis.txt1 Samsung S5P/Exynos SoC series MIPI CSI-2 receiver (MIPI CSIS)
2 -------------------------------------------------------------
6 - compatible : "samsung,s5pv210-csis" for S5PV210 (S5PC110),
7 "samsung,exynos4210-csis" for Exynos4210 (S5PC210),
8 "samsung,exynos4212-csis" for Exynos4212/Exynos4412,
9 "samsung,exynos5250-csis" for Exynos5250;
10 - reg : offset and length of the register set for the device;
11 - interrupts : should contain MIPI CSIS interrupt; the format of the
13 - bus-width : maximum number of data lanes supported (SoC specific);
14 - vddio-supply : MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V);
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/Linux-v6.1/Documentation/devicetree/bindings/
Dxilinx.txt1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
10 Each IP-core has a set of parameters which the FPGA designer can use to
14 device drivers how the IP cores are configured, but it requires the kernel
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
30 xlnx,(parameter2) = <(int-value)>;
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/Linux-v6.1/Documentation/devicetree/bindings/clock/ti/
Ddra7-atl.txt1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
3 The ATL IP is used to generate clock to be used to synchronize baseband and
4 audio codec. A single ATL IP provides four ATL clock instances sharing the same
5 functional clock but can be configured to provide different clocks.
6 ATL can maintain a clock averages to some desired frequency based on the bws/aws
7 signals - can compensate the drift between the two ws signal.
12 Clock tree binding:
13 This binding uses the common clock binding[1].
14 To be able to integrate the ATL clocks with DT clock tree.
16 Since the clock instances are part of a single IP this binding is used as a node
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/Linux-v6.1/drivers/pwm/
Dpwm-tegra.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
15 * The PWM clock frequency is divided by 256 before subdividing it based
16 * on the programmable frequency division value to generate the required
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/Linux-v6.1/Documentation/devicetree/bindings/net/can/
Dmpc5xxx-mscan.txt2 ------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
7 fsl,mpc5200-mscan nodes
8 -----------------------
9 In addition to the required compatible-, reg- and interrupt-properties, you can
10 also specify which clock source shall be used for the controller:
12 - fsl,mscan-clock-source : a string describing the clock source. Valid values
13 are: "ip" for ip bus clock
14 "ref" for reference clock (XTAL)
18 fsl,mpc5121-mscan nodes
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Dgrcan.txt3 The GRCAN and CRHCAN CAN controllers are available in the GRLIB VHDL IP core
12 - name : Should be "GAISLER_GRCAN", "01_03d", "GAISLER_GRHCAN" or "01_034"
14 - reg : Address and length of the register set for the device
16 - freq : Frequency of the external oscillator clock in Hz (the frequency of
19 - interrupts : Interrupt number for this device
23 - systemid : If not present or if the value of the least significant 16 bits
24 of this 32-bit property is smaller than GRCAN_TXBUG_SAFE_GRLIB_VERSION
27 For further information look in the documentation for the GLIB IP core library:
/Linux-v6.1/arch/arc/boot/dts/
Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
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/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dst,stm32-rcc.txt1 STMicroelectronics STM32 Reset and Clock Controller
4 The RCC IP is both a reset and a clock controller.
6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
16 - reg: should be register base and length as documented in the
18 - #reset-cells: 1, see below
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Dqoriq-clock.txt1 * Clock Block on Freescale QorIQ Platforms
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
7 cores and peripheral IP blocks.
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
[all …]
Dadi,axi-clkgen.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Binding for Analog Devices AXI clkgen pcore clock generator
10 - Lars-Peter Clausen <lars@metafoo.de>
11 - Michael Hennerich <michael.hennerich@analog.com>
14 The axi_clkgen IP core is a software programmable clock generator,
22 - adi,axi-clkgen-2.00.a
23 - adi,zynqmp-axi-clkgen-2.00.a
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/ptp/
Dptp-qoriq.txt1 * Freescale QorIQ 1588 timer based PTP clock
5 - compatible Should be "fsl,etsec-ptp" for eTSEC
6 Should be "fsl,fman-ptp-timer" for DPAA FMan
7 Should be "fsl,dpaa2-ptp" for DPAA2
8 Should be "fsl,enetc-ptp" for ENETC
9 - reg Offset and length of the register set for the device
10 - interrupts There should be at least two interrupts. Some devices
13 Clock Properties:
15 - fsl,cksel Timer reference clock source.
16 - fsl,tclk-period Timer reference clock period in nanoseconds.
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Danimeo_ip.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * animeo_ip.dts - Device Tree file for Somfy Animeo IP Boards
5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 /dts-v1/;
12 model = "Somfy Animeo IP";
13 compatible = "somfy,animeo-ip", "atmel,at91sam9260", "atmel,at91sam9";
26 stdout-path = &usart2;
35 clock-frequency = <32768>;
39 clock-frequency = <18432000>;
47 compatible = "atmel,tcb-timer";
[all …]
Dr7s72100-genmai.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-14 Renesas Solutions Corp.
6 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
23 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
24 stdout-path = "serial0:115200n8";
33 #address-cells = <1>;
34 #size-cells = <1>;
[all …]
/Linux-v6.1/include/linux/clk/
Dti.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * TI clock drivers support
10 #include <linux/clk-provider.h>
14 * struct clk_omap_reg - OMAP register declaration
15 * @offset: offset from the master IP module base address
16 * @index: index of the master IP module
26 * struct dpll_data - DPLL registers and integration data
30 * @clk_bypass: struct clk_hw pointer to the clock's bypass clock input
31 * @clk_ref: struct clk_hw pointer to the clock's reference clock input
40 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/spi/
Drockchip-sfc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
11 - Chris Morgan <macromorgan@hotmail.com>
14 - $ref: spi-controller.yaml#
20 The rockchip sfc controller is a standalone IP with version register,
21 and the driver can handle all the feature difference inside the IP
32 - description: Bus Clock
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/timer/
Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
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/Linux-v6.1/arch/arm64/boot/dts/renesas/
Dr8a779f0-spider-cpu.dtsi1 // SPDX-License-Identifier: (GPL-2.0 or MIT)
12 compatible = "renesas,spider-cpu", "renesas,r8a779f0";
20 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
21 stdout-path = "serial0:115200n8";
35 reg_1p8v: regulator-1p8v {
36 compatible = "regulator-fixed";
37 regulator-name = "fixed-1.8V";
38 regulator-min-microvolt = <1800000>;
39 regulator-max-microvolt = <1800000>;
40 regulator-boot-on;
[all …]
Dr8a779g0-white-hawk-cpu.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
16 compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0";
24 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
25 stdout-path = "serial0:921600n8";
29 compatible = "gpio-keys";
31 pinctrl-0 = <&keys_pins>;
32 pinctrl-names = "default";
[all …]
/Linux-v6.1/drivers/clk/xilinx/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
10 register set. This driver also configures the frequency based on the
11 clock information from the logicoreIP register set.
25 Support for the Xilinx Clocking Wizard IP core clock generator.
27 This driver supports the Xilinx clocking wizard programmable clock
/Linux-v6.1/Documentation/devicetree/bindings/clock/sifive/
Dfu540-prci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
15 On the FU540 family of SoCs, most system-wide clock and reset integration
16 is via the PRCI IP block.
17 The clock consumer should specify the desired clock via the clock ID
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