Lines Matching +full:ip +full:- +full:clock +full:- +full:frequency

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
11   - Sagar Kadam <sagar.kadam@sifive.com>
12   - Paul Walmsley  <paul.walmsley@sifive.com>
15   On the FU540 family of SoCs, most system-wide clock and reset integration
16   is via the PRCI IP block.
17   The clock consumer should specify the desired clock via the clock ID
18   macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
27     const: sifive,fu540-c000-prci
34       - description: high frequency clock.
35       - description: RTL clock.
37   clock-names:
39       - const: hfclk
40       - const: rtcclk
42   "#clock-cells":
46   - compatible
47   - reg
48   - clocks
49   - "#clock-cells"
54   - |
55     prci: clock-controller@10000000 {
56       compatible = "sifive,fu540-c000-prci";
59       #clock-cells = <1>;