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/Linux-v6.1/Documentation/devicetree/bindings/iommu/
Dqcom,iommu.txt1 * QCOM IOMMU v1 Implementation
3 Qualcomm "B" family devices which are not compatible with arm-smmu have
4 a similar looking IOMMU but without access to the global register space,
6 to non-secure vs secure interrupt line.
10 - compatible : Should be one of:
12 "qcom,msm8916-iommu"
14 Followed by "qcom,msm-iommu-v1".
16 - clock-names : Should be a pair of "iface" (required for IOMMUs
20 - clocks : Phandles for respective clocks described by
21 clock-names.
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Dsprd,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/iommu/sprd,iommu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Unisoc IOMMU and Multi-media MMU
11 - Chunyan Zhang <zhang.lyra@gmail.com>
16 - sprd,iommu-v1
18 "#iommu-cells":
21 Unisoc IOMMUs are all single-master IOMMU devices, therefore no
24 Documentation/devicetree/bindings/iommu/iommu.txt
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Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
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/Linux-v6.1/drivers/iommu/arm/arm-smmu/
Dqcom_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c
13 #include <linux/dma-mapping.h>
17 #include <linux/io-64-nonatomic-hi-lo.h>
18 #include <linux/io-pgtable.h>
19 #include <linux/iommu.h>
34 #include "arm-smmu.h"
48 /* IOMMU core code handle */
49 struct iommu_device iommu; member
55 struct qcom_iommu_ctx *ctxs[]; /* indexed by asid-1 */
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/Linux-v6.1/drivers/iommu/
Dmtk_iommu_v1.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for MTK architected m4u v1 implementations
5 * Copyright (c) 2015-2016 MediaTek Inc.
8 * Based on driver/iommu/mtk_iommu.c
14 #include <linux/dma-mapping.h>
18 #include <linux/iommu.h>
29 #include <asm/dma-iommu.h>
30 #include <dt-bindings/memory/mtk-memory-port.h>
31 #include <dt-bindings/memory/mt2701-larb-port.h>
76 #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7))
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 # The IOVA library may also be used by non-IOMMU_API users
6 # The IOASID library may also be used by non-IOMMU_API users
15 bool "IOMMU Hardware Support"
26 menu "Generic IOMMU Pagetable Support"
39 sizes at both stage-1 and stage-2, as well as address spaces
40 up to 48-bits in size.
46 Enable self-tests for LPAE page table allocator. This performs
47 a series of page-table consistency checks during boot.
56 Enable support for the ARM Short-descriptor pagetable format.
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Dsprd-iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Unisoc IOMMU driver
11 #include <linux/dma-mapping.h>
13 #include <linux/iommu.h>
51 * struct sprd_iommu_device - high-level sprd IOMMU device representation,
54 * @ver: sprd IOMMU IP version
60 * @iommu: IOMMU core representation
61 * @group: IOMMU group
62 * @eb: gate clock which controls IOMMU access
70 struct iommu_device iommu; member
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Dexynos-iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/dma-mapping.h>
15 #include <linux/iommu.h>
37 #define SECT_MASK (~(SECT_SIZE - 1))
38 #define LPAGE_MASK (~(LPAGE_SIZE - 1))
39 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
54 * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces
61 static short PG_ENT_SHIFT = -1;
97 #define section_offs(iova) (iova & (SECT_SIZE - 1))
99 #define lpage_offs(iova) (iova & (LPAGE_SIZE - 1))
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/Linux-v6.1/Documentation/devicetree/bindings/powerpc/fsl/
Dpamu.txt5 The PAMU is an I/O MMU that provides device-to-memory access control and
10 - compatible : <string>
11 First entry is a version-specific string, such as
12 "fsl,pamu-v1.0". The second is "fsl,pamu".
13 - ranges : <prop-encoded-array>
18 PAMU v1.0, on an SOC that has five PAMU devices, the size
20 - interrupts : <prop-encoded-array>
25 - #address-cells: <u32>
27 - #size-cells : <u32>
31 - reg : <prop-encoded-array>
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Draideng.txt3 RAID Engine nodes are defined to describe on-chip RAID accelerators. Each RAID
11 - compatible: Should contain "fsl,raideng-v1.0" as the value
15 - reg: offset and length of the register set for the device
16 - ranges: standard ranges property specifying the translation
22 compatible = "fsl,raideng-v1.0";
23 #address-cells = <1>;
24 #size-cells = <1>;
30 There must be a sub-node for each job queue present in RAID Engine
31 This node must be a sub-node of the main RAID Engine node
33 - compatible: Should contain "fsl,raideng-v1.0-job-queue" as the value
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/Linux-v6.1/arch/arm64/boot/dts/arm/
Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 clock-frequency = <50000000>;
14 #address-cells = <1>;
15 #size-cells = <1>;
19 frame-number = <1>;
31 #mbox-cells = <1>;
33 clock-names = "apb_pclk";
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Dfvp-base-revc.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
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/Linux-v6.1/arch/arm/boot/dts/
Dqcom-apq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
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Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
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/Linux-v6.1/arch/powerpc/boot/dts/fsl/
Dp5020si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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Dp3041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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Dp2041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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Dp5040si-post.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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Dp4080si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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/Linux-v6.1/arch/arm64/boot/dts/qcom/
Dmsm8916.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8916.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
13 #include <dt-bindings/thermal/thermal.h>
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/Linux-v6.1/drivers/iommu/amd/
Dinit.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
20 #include <linux/amd-iommu.h>
25 #include <asm/pci-direct.h>
26 #include <asm/iommu.h>
99 * structure describing one IOMMU in the ACPI table. Typically followed by one
119 * A device entry describing which devices a specific IOMMU translates and
137 * An AMD IOMMU memory definition structure. It defines things like exclusion
183 /* IOMMUs have a non-present cache? */
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/Linux-v6.1/Documentation/driver-api/
Dvfio.rst2 VFIO - "Virtual Function I/O" [1]_
7 allotted. This includes x86 hardware with AMD-Vi and Intel VT-d,
9 systems such as Freescale PAMU. The VFIO driver is an IOMMU/device
11 a secure, IOMMU protected environment. In other words, this allows
12 safe [2]_, non-privileged, userspace drivers.
19 bare-metal device drivers [3]_.
22 field, also benefit from low-overhead, direct device access from
23 userspace. Examples include network adapters (often non-TCP/IP based)
27 which has no notion of IOMMU protection, limited interrupt support,
36 ---------------------------
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/Linux-v6.1/drivers/vfio/
Dvfio_iommu_type1.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * VFIO: IOMMU DMA mapping support for Type1 IOMMU
12 * We arbitrarily define a Type1 IOMMU as one matching the below code.
13 * It could be called the x86 IOMMU as it's designed for AMD-Vi & Intel
14 * VT-d, but that makes it harder to re-use as theoretically anyone
15 * implementing a similar IOMMU could make use of this. We expect the
16 * IOMMU to support the IOMMU API and have few to no restrictions around
17 * the IOVA range that can be mapped. The Type1 IOMMU is currently
19 * userspace pages pinned into memory. We also assume devices and IOMMU
20 * domains are PCI based as the IOMMU API is still centered around a
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/Linux-v6.1/drivers/net/ethernet/toshiba/
Dps3_gelic_net.c1 // SPDX-License-Identifier: GPL-2.0-or-later
31 #include <linux/dma-mapping.h>
63 card->irq_mask |= GELIC_CARD_RXINT; in gelic_card_rx_irq_on()
64 gelic_card_set_irq_mask(card, card->irq_mask); in gelic_card_rx_irq_on()
68 card->irq_mask &= ~GELIC_CARD_RXINT; in gelic_card_rx_irq_off()
69 gelic_card_set_irq_mask(card, card->irq_mask); in gelic_card_rx_irq_off()
81 &card->ether_port_status, &v2); in gelic_card_get_ether_port_status()
84 ether_netdev = card->netdev[GELIC_PORT_ETHERNET_0]; in gelic_card_get_ether_port_status()
85 if (card->ether_port_status & GELIC_LV1_ETHER_LINK_UP) in gelic_card_get_ether_port_status()
93 * gelic_descr_get_status -- returns the status of a descriptor
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/Linux-v6.1/Documentation/admin-guide/media/
Domap4_camera.rst1 .. SPDX-License-Identifier: GPL-2.0
11 ------------
16 - Interfaces (2 Interfaces: CSI2-A & CSI2-B/CCP2)
17 - ISP (Image Signal Processor)
18 - SIMCOP (Still Image Coprocessor)
25 This driver is supporting **only** the CSI2-A/B interfaces for now.
29 except that it doesn't need an IOMMU now for ISS buffers memory mapping.
34 ----------------
36 - OMAP4430SDP, w/ ES2.1 GP & SEVM4430-CAM-V1-0 (Contains IMX060 & OV5640, in
39 - TI Blaze MDP, w/ OMAP4430 ES2.2 EMU (Contains 1 IMX060 & 2 OV5650 sensors, in
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