Searched +full:interrupt +full:- +full:parent (Results 1 – 25 of 1066) sorted by relevance
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/Linux-v5.4/arch/arm/boot/dts/ |
D | arm-realview-pba8.dts | 23 /dts-v1/; 24 #include "arm-realview-pbx.dtsi" 27 model = "ARM RealView Platform Baseboard for Cortex-A8"; 28 compatible = "arm,realview-pba8"; 32 #address-cells = <1>; 33 #size-cells = <0>; 34 enable-method = "arm,realview-smp"; 38 compatible = "arm,cortex-a8"; 44 compatible = "arm,cortex-a8-pmu"; 45 interrupt-parent = <&intc>; [all …]
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D | arm-realview-pbx-a9.dts | 23 /dts-v1/; 24 #include "arm-realview-pbx.dtsi" 28 * This is the RealView Platform Baseboard Explore for Cortex-A9 31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9"; 35 #address-cells = <1>; 36 #size-cells = <0>; 37 enable-method = "arm,realview-smp"; 39 cpu-map { 51 compatible = "arm,cortex-a9"; 53 next-level-cache = <&L2>; [all …]
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D | arm-realview-eb.dts | 23 /dts-v1/; 24 #include <dt-bindings/interrupt-controller/irq.h> 25 #include <dt-bindings/gpio/gpio.h> 26 #include "arm-realview-eb.dtsi" 30 compatible = "arm,realview-eb"; 35 * ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache 39 * qemu-system-arm -M realview-eb 40 * Unless specified, QEMU will emulate an ARM926EJ-S core tile. 41 * Switches -cpu arm1136 or -cpu arm1176 emulates the other 45 #address-cells = <1>; [all …]
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D | arm-realview-eb-mp.dtsi | 23 #include <dt-bindings/interrupt-controller/irq.h> 24 #include <dt-bindings/gpio/gpio.h> 25 #include "arm-realview-eb.dtsi" 30 * and Cortex-A9 MPCore. 34 #address-cells = <1>; 35 #size-cells = <1>; 36 compatible = "arm,realview-eb-soc", "simple-bus"; 40 /* Primary interrupt controller in the test chip */ 41 intc: interrupt-controller@1f000100 { 42 compatible = "arm,eb11mp-gic"; [all …]
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D | spear600.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 7 #address-cells = <1>; 8 #size-cells = <1>; 12 #address-cells = <0>; 13 #size-cells = <0>; 16 compatible = "arm,arm926ej-s"; 27 #address-cells = <1>; 28 #size-cells = <1>; 29 compatible = "simple-bus"; 32 vic0: interrupt-controller@f1100000 { [all …]
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D | s5pv210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. 19 #include <dt-bindings/clock/s5pv210.h> 20 #include <dt-bindings/clock/s5pv210-audss.h> 23 #address-cells = <1>; 24 #size-cells = <1>; 45 #address-cells = <1>; 46 #size-cells = <0>; 50 compatible = "arm,cortex-a8"; 56 compatible = "simple-bus"; [all …]
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/Linux-v5.4/Documentation/devicetree/bindings/edac/ |
D | socfpga-eccmgr.txt | 8 - compatible : Should be "altr,socfpga-ecc-manager" 9 - #address-cells: must be 1 10 - #size-cells: must be 1 11 - ranges : standard definition, should translate from local addresses 17 - compatible : Should be "altr,socfpga-l2-ecc" 18 - reg : Address and size for ECC error interrupt clear registers. 19 - interrupts : Should be single bit error interrupt, then double bit error 20 interrupt. Note the rising edge type. 24 - compatible : Should be "altr,socfpga-ocram-ecc" 25 - reg : Address and size for ECC error interrupt clear registers. [all …]
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/Linux-v5.4/arch/powerpc/boot/dts/ |
D | fsp2.dts | 12 /dts-v1/; 15 #address-cells = <2>; 16 #size-cells = <1>; 19 dcr-parent = <&{/cpus/cpu@0}>; 28 #address-cells = <1>; 29 #size-cells = <0>; 35 clock-frequency = <0>; /* Filled in by cuboot */ 36 timebase-frequency = <0>; /* Filled in by cuboot */ 37 i-cache-line-size = <32>; 38 d-cache-line-size = <32>; [all …]
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D | mpc8377_wlan.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 5 * Copyright 2007-2009 Freescale Semiconductor Inc. 9 /dts-v1/; 13 #address-cells = <1>; 14 #size-cells = <1>; 27 #address-cells = <1>; 28 #size-cells = <0>; 33 d-cache-line-size = <32>; 34 i-cache-line-size = <32>; 35 d-cache-size = <32768>; [all …]
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D | tqm8560.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 9 /dts-v1/; 14 #address-cells = <1>; 15 #size-cells = <1>; 27 #address-cells = <1>; 28 #size-cells = <0>; 33 d-cache-line-size = <32>; 34 i-cache-line-size = <32>; 35 d-cache-size = <32768>; 36 i-cache-size = <32768>; [all …]
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/Linux-v5.4/arch/mips/boot/dts/brcm/ |
D | bcm7358.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #address-cells = <1>; 4 #size-cells = <1>; 8 #address-cells = <1>; 9 #size-cells = <0>; 11 mips-hpt-frequency = <375000000>; 24 cpu_intc: interrupt-controller { 25 #address-cells = <0>; 26 compatible = "mti,cpu-interrupt-controller"; 28 interrupt-controller; [all …]
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D | bcm7346.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #address-cells = <1>; 4 #size-cells = <1>; 8 #address-cells = <1>; 9 #size-cells = <0>; 11 mips-hpt-frequency = <163125000>; 30 cpu_intc: interrupt-controller { 31 #address-cells = <0>; 32 compatible = "mti,cpu-interrupt-controller"; 34 interrupt-controller; [all …]
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D | bcm7435.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #address-cells = <1>; 4 #size-cells = <1>; 8 #address-cells = <1>; 9 #size-cells = <0>; 11 mips-hpt-frequency = <175625000>; 42 cpu_intc: interrupt-controller { 43 #address-cells = <0>; 44 compatible = "mti,cpu-interrupt-controller"; 46 interrupt-controller; [all …]
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D | bcm7425.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #address-cells = <1>; 4 #size-cells = <1>; 8 #address-cells = <1>; 9 #size-cells = <0>; 11 mips-hpt-frequency = <163125000>; 30 cpu_intc: interrupt-controller { 31 #address-cells = <0>; 32 compatible = "mti,cpu-interrupt-controller"; 34 interrupt-controller; [all …]
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D | bcm7360.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #address-cells = <1>; 4 #size-cells = <1>; 8 #address-cells = <1>; 9 #size-cells = <0>; 11 mips-hpt-frequency = <375000000>; 24 cpu_intc: interrupt-controller { 25 #address-cells = <0>; 26 compatible = "mti,cpu-interrupt-controller"; 28 interrupt-controller; [all …]
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D | bcm7420.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #address-cells = <1>; 4 #size-cells = <1>; 8 #address-cells = <1>; 9 #size-cells = <0>; 11 mips-hpt-frequency = <93750000>; 30 cpu_intc: interrupt-controller { 31 #address-cells = <0>; 32 compatible = "mti,cpu-interrupt-controller"; 34 interrupt-controller; [all …]
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D | bcm7362.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #address-cells = <1>; 4 #size-cells = <1>; 8 #address-cells = <1>; 9 #size-cells = <0>; 11 mips-hpt-frequency = <375000000>; 30 cpu_intc: interrupt-controller { 31 #address-cells = <0>; 32 compatible = "mti,cpu-interrupt-controller"; 34 interrupt-controller; [all …]
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D | bcm7125.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #address-cells = <1>; 4 #size-cells = <1>; 8 #address-cells = <1>; 9 #size-cells = <0>; 11 mips-hpt-frequency = <202500000>; 30 cpu_intc: interrupt-controller { 31 #address-cells = <0>; 32 compatible = "mti,cpu-interrupt-controller"; 34 interrupt-controller; [all …]
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/Linux-v5.4/arch/arm64/boot/dts/xilinx/ |
D | zynqmp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * (C) Copyright 2014 - 2015, Xilinx, Inc. 17 #address-cells = <2>; 18 #size-cells = <2>; 21 #address-cells = <1>; 22 #size-cells = <0>; 25 compatible = "arm,cortex-a53"; 27 enable-method = "psci"; 28 operating-points-v2 = <&cpu_opp_table>; 30 cpu-idle-states = <&CPU_SLEEP_0>; [all …]
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/Linux-v5.4/arch/mips/boot/dts/ingenic/ |
D | jz4770.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #include <dt-bindings/clock/jz4770-cgu.h> 6 #address-cells = <1>; 7 #size-cells = <1>; 10 cpuintc: interrupt-controller { 11 #address-cells = <0>; 12 #interrupt-cells = <1>; 13 interrupt-controller; 14 compatible = "mti,cpu-interrupt-controller"; 17 intc: interrupt-controller@10001000 { [all …]
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D | jz4740.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/jz4740-cgu.h> 5 #address-cells = <1>; 6 #size-cells = <1>; 9 cpuintc: interrupt-controller { 10 #address-cells = <0>; 11 #interrupt-cells = <1>; 12 interrupt-controller; 13 compatible = "mti,cpu-interrupt-controller"; 16 intc: interrupt-controller@10001000 { [all …]
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D | jz4780.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/jz4780-cgu.h> 3 #include <dt-bindings/dma/jz4780-dma.h> 6 #address-cells = <1>; 7 #size-cells = <1>; 10 cpuintc: interrupt-controller { 11 #address-cells = <0>; 12 #interrupt-cells = <1>; 13 interrupt-controller; 14 compatible = "mti,cpu-interrupt-controller"; [all …]
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/Linux-v5.4/drivers/of/ |
D | irq.c | 1 // SPDX-License-Identifier: GPL-2.0+ 6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 8 * Copyright (C) 1996-2001 Cort Dougan 13 * device tree to actual irq numbers on an interrupt controller 29 * irq_of_parse_and_map - Parse and map an interrupt into linux virq space 30 * @dev: Device node of the device whose interrupt is to be mapped 31 * @index: Index of the interrupt to map 48 * of_irq_find_parent - Given a device node, find its interrupt parent node 51 * Returns a pointer to the interrupt parent node, or NULL if the interrupt 52 * parent could not be determined. [all …]
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/Linux-v5.4/Documentation/devicetree/bindings/interrupt-controller/ |
D | interrupts.txt | 1 Specifying interrupt information for devices 4 1) Interrupt client nodes 5 ------------------------- 8 "interrupts" property, an "interrupts-extended" property, or both. If both are 11 properties contain a list of interrupt specifiers, one per output interrupt. The 12 format of the interrupt specifier is determined by the interrupt controller to 16 interrupt-parent = <&intc1>; 19 The "interrupt-parent" property is used to specify the controller to which 20 interrupts are routed and contains a single phandle referring to the interrupt 22 interrupt client node or in any of its parent nodes. Interrupts listed in the [all …]
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D | marvell,icu.txt | 1 Marvell ICU Interrupt Controller 2 -------------------------------- 4 The Marvell ICU (Interrupt Consolidation Unit) controller is 5 responsible for collecting all wired-interrupt sources in the CP and 6 communicating them to the GIC in the AP, the unit translates interrupt 13 - compatible: Should be "marvell,cp110-icu" 15 - reg: Should contain ICU registers location and length. 17 Subnodes: Each group of interrupt is declared as a subnode of the ICU, 22 - compatible: Should be one of: 23 * "marvell,cp110-icu-nsr" [all …]
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