| /Linux-v6.1/drivers/media/dvb-frontends/ |
| D | stb0899_algo.c | 50 struct stb0899_internal *internal = &state->internal;
55 return stb0899_calc_srate(internal->master_clk, sfr);
122 struct stb0899_internal *internal = &state->internal; in stb0899_carr_width() local
124 return (internal->srate + (internal->srate * internal->rolloff) / 100); in stb0899_carr_width()
133 struct stb0899_internal *internal = &state->internal; in stb0899_first_subrange() local
148 internal->sub_range = min(internal->srch_range, range); in stb0899_first_subrange()
150 internal->sub_range = 0; in stb0899_first_subrange()
152 internal->freq = params->freq; in stb0899_first_subrange()
153 internal->tuner_offst = 0L; in stb0899_first_subrange()
154 internal->sub_dir = 1; in stb0899_first_subrange()
[all …]
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| D | stb0899_drv.c | 558 struct stb0899_internal *internal = &state->internal; in stb0899_set_mclk() local
566 internal->master_clk = stb0899_get_mclk(state); in stb0899_set_mclk()
568 dprintk(state->verbose, FE_DEBUG, 1, "MasterCLOCK=%d", internal->master_clk); in stb0899_set_mclk()
630 struct stb0899_internal *internal = &state->internal; in stb0899_init_calc() local
640 internal->t_agc1 = 0; in stb0899_init_calc()
641 internal->t_agc2 = 0; in stb0899_init_calc()
642 internal->master_clk = master_clk; in stb0899_init_calc()
643 internal->mclk = master_clk / 65536L; in stb0899_init_calc()
644 internal->rolloff = stb0899_get_alpha(state); in stb0899_init_calc()
648 internal->agc_gain = 8154; in stb0899_init_calc()
[all …]
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| /Linux-v6.1/include/uapi/misc/ |
| D | habanalabs.h | 39 * The external queues (PCI DMA channels) MUST be before the internal queues
40 * and each group (PCI DMA channels and internal) must be contiguous inside
52 GOYA_QUEUE_ID_MME = 6, /* Internal queues start here */
67 * Except one CPU queue, all the rest are internal queues.
80 GAUDI_QUEUE_ID_DMA_2_0 = 9, /* internal */
81 GAUDI_QUEUE_ID_DMA_2_1 = 10, /* internal */
82 GAUDI_QUEUE_ID_DMA_2_2 = 11, /* internal */
83 GAUDI_QUEUE_ID_DMA_2_3 = 12, /* internal */
84 GAUDI_QUEUE_ID_DMA_3_0 = 13, /* internal */
85 GAUDI_QUEUE_ID_DMA_3_1 = 14, /* internal */
[all …]
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| /Linux-v6.1/Documentation/driver-api/ |
| D | basics.rst | 8 :internal:
14 :internal:
22 :internal:
28 :internal:
31 :internal:
34 :internal:
43 :internal:
52 :internal:
55 :internal:
60 Internal Functions
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| D | w1.rst | 7 W1 API internal to the kernel
16 :internal:
24 :internal:
37 W1 internal initialization for master devices.
40 :internal:
45 W1 internal initialization for master devices.
56 :internal:
67 :internal:
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| D | infiniband.rst | 14 :internal:
77 :internal:
90 :internal:
93 :internal:
99 :internal:
102 :internal:
105 :internal:
108 :internal:
114 :internal:
117 :internal:
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| D | infrastructure.rst | 8 :internal:
15 :internal:
30 :internal:
39 :internal:
57 :internal:
63 :internal:
78 :internal:
|
| /Linux-v6.1/Documentation/driver-api/surface_aggregator/ |
| D | internal-api.rst | 4 Internal API Documentation
15 :internal:
18 :internal:
21 :internal:
24 :internal:
27 :internal:
34 :internal:
37 :internal:
44 :internal:
47 :internal:
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| /Linux-v6.1/Documentation/devicetree/bindings/net/dsa/ |
| D | nxp,sja1105.yaml | 39 # Optional container node for the 2 internal MDIO buses of the SJA1110
40 # (one for the internal 100base-T1 PHYs and the other for the single
92 rx-internal-delay-ps:
93 $ref: "#/$defs/internal-delay-ps"
94 tx-internal-delay-ps:
95 $ref: "#/$defs/internal-delay-ps"
102 internal-delay-ps:
131 rx-internal-delay-ps = <0>;
132 tx-internal-delay-ps = <0>;
139 rx-internal-delay-ps = <0>;
[all …]
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| D | microchip,lan937x.yaml | 54 rx-internal-delay-ps:
57 tx-internal-delay-ps:
97 phy-mode = "internal";
104 phy-mode = "internal";
111 phy-mode = "internal";
118 phy-mode = "internal";
125 tx-internal-delay-ps = <2000>;
126 rx-internal-delay-ps = <2000>;
139 tx-internal-delay-ps = <2000>;
140 rx-internal-delay-ps = <2000>;
[all …]
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| D | qca8k.yaml | 14 describing a port needs to have a valid phandle referencing the internal PHY
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
17 the switch node and declare the phandle for the port, referencing the internal
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
19 the MDIO master is used for communication. Mixed external and internal
63 description: Qca8k switch have an internal mdio to access switch port.
65 internal mdio access is used.
66 With the legacy mapping the reg corresponding to the internal
235 phy-mode = "internal";
242 phy-mode = "internal";
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| /Linux-v6.1/Documentation/networking/ |
| D | tipc.rst | 131 :internal:
134 :internal:
137 :internal:
140 :internal:
143 :internal:
149 :internal:
152 :internal:
158 :internal:
164 :internal:
170 :internal:
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| D | kapi.rst | 12 :internal:
18 :internal:
21 :internal:
48 :internal:
102 :internal:
105 :internal:
114 :internal:
123 :internal:
129 :internal:
135 :internal:
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| /Linux-v6.1/lib/ |
| D | test_bpf.c | 60 INTERNAL = BIT(7), /* Extended instruction set. */ enumerator
63 #define TEST_TYPE_MASK (CLASSIC | INTERNAL)
3717 INTERNAL,
3733 INTERNAL,
3750 INTERNAL,
3767 INTERNAL,
3929 INTERNAL,
4075 INTERNAL,
4208 INTERNAL,
4274 INTERNAL,
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| /Linux-v6.1/arch/powerpc/include/asm/ |
| D | cpm1.h | 8 * through the MPC8xx internal memory map. See immap.h for details.
84 uint smc_rstate; /* Internal */
85 uint smc_idp; /* Internal */
86 ushort smc_rbptr; /* Internal */
87 ushort smc_ibc; /* Internal */
88 uint smc_rxtmp; /* Internal */
89 uint smc_tstate; /* Internal */
90 uint smc_tdp; /* Internal */
91 ushort smc_tbptr; /* Internal */
92 ushort smc_tbc; /* Internal */
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| D | ipic.h | 28 #define IPIC_SIPNR_H 0x08 /* System Internal Interrupt Pending Register (HIGH) */
29 #define IPIC_SIPNR_L 0x0C /* System Internal Interrupt Pending Register (LOW) */
30 #define IPIC_SIPRR_A 0x10 /* System Internal Interrupt group A Priority Register */
31 #define IPIC_SIPRR_B 0x14 /* System Internal Interrupt group B Priority Register */
32 #define IPIC_SIPRR_C 0x18 /* System Internal Interrupt group C Priority Register */
33 #define IPIC_SIPRR_D 0x1C /* System Internal Interrupt group D Priority Register */
34 #define IPIC_SIMSR_H 0x20 /* System Internal Interrupt Mask Register (HIGH) */
35 #define IPIC_SIMSR_L 0x24 /* System Internal Interrupt Mask Register (LOW) */
36 #define IPIC_SICNR 0x28 /* System Internal Interrupt Control Register */
45 #define IPIC_SIFCR_H 0x50 /* System Internal Interrupt Force Register (HIGH) */
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| D | cpm2.h | 7 * All CPM control and status is available through the CPM2 internal
173 uint smc_rstate; /* Internal */
174 uint smc_idp; /* Internal */
175 ushort smc_rbptr; /* Internal */
176 ushort smc_ibc; /* Internal */
177 uint smc_rxtmp; /* Internal */
178 uint smc_tstate; /* Internal */
179 uint smc_tdp; /* Internal */
180 ushort smc_tbptr; /* Internal */
181 ushort smc_tbc; /* Internal */
[all …]
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| /Linux-v6.1/drivers/media/pci/cx23885/ |
| D | altera-ci.c | 111 struct fpga_internal *internal; member
119 struct fpga_internal *internal; member
129 /* internal params node */
131 /* pointer for internal params, one for each pair of CI's */
132 struct fpga_internal *internal; member
136 /* first internal params */
151 (temp_chip->internal->dev != dev)) in find_inode()
183 if (temp_chip->internal != NULL) { in find_dinode()
184 temp_int = temp_chip->internal; in find_dinode()
198 static void remove_inode(struct fpga_internal *internal) in remove_inode() argument
[all …]
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| /Linux-v6.1/Documentation/core-api/ |
| D | kernel-api.rst | 10 :internal:
43 :internal:
58 :internal:
61 :internal:
64 :internal:
85 :internal:
88 :internal:
125 :internal:
154 :internal:
172 :internal:
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| /Linux-v6.1/include/linux/ |
| D | average.h | 30 unsigned long internal; \
42 e->internal = 0; \
51 return e->internal >> (_precision); \
56 unsigned long internal = READ_ONCE(e->internal); \
65 WRITE_ONCE(e->internal, internal ? \
66 (((internal << weight_rcp) - internal) + \
|
| /Linux-v6.1/Documentation/devicetree/bindings/net/ |
| D | ti,dp83822.yaml | 51 rx-internal-delay-ps:
54 Setting this property to a non-zero number sets the RX internal delay
55 for the PHY. The internal delay for the PHY is fixed to 3.5ns relative
58 tx-internal-delay-ps:
61 Setting this property to a non-zero number sets the TX internal delay
62 for the PHY. The internal delay for the PHY is fixed to 3.5ns relative
77 rx-internal-delay-ps = <1>;
78 tx-internal-delay-ps = <1>;
|
| D | adi,adin.yaml | 19 adi,rx-internal-delay-ps:
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
44 the 125MHz clocks based on its internal state.
68 adi,rx-internal-delay-ps = <1800>;
69 adi,tx-internal-delay-ps = <2200>;
|
| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.c | 284 static void rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mg… in rn_dump_clk_registers_internal() argument
288 internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT); in rn_dump_clk_registers_internal()
289 internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL); in rn_dump_clk_registers_internal()
291 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL); //dcf deep sleep divider in rn_dump_clk_registers_internal()
292 internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS); in rn_dump_clk_registers_internal()
294 internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT); in rn_dump_clk_registers_internal()
295 internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL); in rn_dump_clk_registers_internal()
297 internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT); in rn_dump_clk_registers_internal()
298 internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL); in rn_dump_clk_registers_internal()
300 internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT); in rn_dump_clk_registers_internal()
[all …]
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | vg_clk_mgr.c | 218 static void vg_dump_clk_registers_internal(struct dcn301_clk_internal *internal, struct clk_mgr *cl… in vg_dump_clk_registers_internal() argument
222 internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK3_CURRENT_CNT); in vg_dump_clk_registers_internal()
223 internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_BYPASS_CNTL); in vg_dump_clk_registers_internal()
225 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_DS_CNTL); //dcf deep sleep divider in vg_dump_clk_registers_internal()
226 internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_0_CLK1_CLK3_ALLOW_DS); in vg_dump_clk_registers_internal()
228 internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK1_CURRENT_CNT); in vg_dump_clk_registers_internal()
229 internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK1_BYPASS_CNTL); in vg_dump_clk_registers_internal()
231 internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK2_CURRENT_CNT); in vg_dump_clk_registers_internal()
232 internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK2_BYPASS_CNTL); in vg_dump_clk_registers_internal()
234 internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK0_CURRENT_CNT); in vg_dump_clk_registers_internal()
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| /Linux-v6.1/include/dt-bindings/memory/ |
| D | tegra194-mc.h | 147 /* MSS internal memqual MIU7 read clients */
149 /* MSS internal memqual MIU7 write clients */
261 /* MSS internal memqual MIU0 read clients */
263 /* MSS internal memqual MIU0 write clients */
265 /* MSS internal memqual MIU1 read clients */
267 /* MSS internal memqual MIU1 write clients */
269 /* MSS internal memqual MIU2 read clients */
271 /* MSS internal memqual MIU2 write clients */
273 /* MSS internal memqual MIU3 read clients */
275 /* MSS internal memqual MIU3 write clients */
[all …]
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