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/Linux-v5.10/Documentation/devicetree/bindings/interconnect/
Dinterconnect.txt1 Interconnect Provider Device Tree Bindings
4 The purpose of this document is to define a common set of generic interconnect
8 = interconnect providers =
10 The interconnect provider binding is intended to represent the interconnect
11 controllers in the system. Each provider registers a set of interconnect
12 nodes, which expose the interconnect related capabilities of the interconnect
14 etc. The consumer drivers set constraints on interconnect path (or endpoints)
15 depending on the use case. Interconnect providers can also be interconnect
20 - compatible : contains the interconnect provider compatible string
21 - #interconnect-cells : number of cells in a interconnect specifier needed to
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Dqcom,msm8916.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,msm8916.yaml#
7 title: Qualcomm MSM8916 Network-On-Chip interconnect
13 The Qualcomm MSM8916 interconnect providers support adjusting the
26 '#interconnect-cells':
42 - '#interconnect-cells'
52 bimc: interconnect@400000 {
55 #interconnect-cells = <1>;
61 pcnoc: interconnect@500000 {
64 #interconnect-cells = <1>;
70 snoc: interconnect@580000 {
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Dqcom,qcs404.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,qcs404.yaml#
7 title: Qualcomm QCS404 Network-On-Chip interconnect
13 The Qualcomm QCS404 interconnect providers support adjusting the
26 '#interconnect-cells':
42 - '#interconnect-cells'
52 bimc: interconnect@400000 {
55 #interconnect-cells = <1>;
61 pnoc: interconnect@500000 {
64 #interconnect-cells = <1>;
70 snoc: interconnect@580000 {
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Dqcom,rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect
14 RPMh interconnect providers support system bandwidth requirements through
71 '#interconnect-cells':
78 this interconnect to send RPMh commands.
88 - '#interconnect-cells'
95 #include <dt-bindings/interconnect/qcom,sdm845.h>
97 mem_noc: interconnect@1380000 {
100 #interconnect-cells = <1>;
104 mmss_noc: interconnect@1740000 {
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Dqcom,osm-l3.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
7 title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
14 The OSM L3 interconnect provider aggregates the L3 bandwidth requests
38 '#interconnect-cells':
46 - '#interconnect-cells'
56 osm_l3: interconnect@17d41000 {
63 #interconnect-cells = <1>;
Dqcom,msm8974.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,msm8974.yaml#
7 title: Qualcomm MSM8974 Network-On-Chip Interconnect
13 The Qualcomm MSM8974 interconnect providers support setting system
29 '#interconnect-cells':
45 - '#interconnect-cells'
55 bimc: interconnect@fc380000 {
58 #interconnect-cells = <1>;
Dfsl,imx8m-noc.yaml4 $id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#
22 interconnect IPs into imx SOCs.
55 '#interconnect-cells':
57 If specified then also act as an interconnect provider. Should only be
70 #include <dt-bindings/interconnect/imx8mm.h>
73 noc: interconnect@32700000 {
77 #interconnect-cells = <1>;
/Linux-v5.10/Documentation/driver-api/
Dinterconnect.rst4 Generic System Interconnect Subsystem
16 The interconnect bus is hardware with configurable parameters, which can be
18 An example of interconnect buses are the interconnects between various
22 Below is a simplified diagram of a real-world SoC interconnect bus topology.
55 Interconnect provider is the software definition of the interconnect hardware.
56 The interconnect providers on the above diagram are M NoC, S NoC, C NoC, P NoC
59 Interconnect node is the software definition of the interconnect hardware
60 port. Each interconnect provider consists of multiple interconnect nodes,
61 which are connected to other SoC components including other interconnect
63 called an interconnect node, which belongs to the Mem NoC interconnect provider.
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/Linux-v5.10/Documentation/devicetree/bindings/bus/
Dti-sysc.txt1 Texas Instruments sysc interconnect target module wrapper binding
3 Texas Instruments SoCs can have a generic interconnect target module
5 interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc
8 of the interconnect.
10 Each interconnect target module can have one or more devices connected to
11 it. There is a set of control registers for managing interconnect target
12 module clocks, idle modes and interconnect level resets for the module.
15 space of the first child device IP block managed by the interconnect
43 - reg shall have register areas implemented for the interconnect
47 interconnect target module in question such as
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Dbaikal,bt1-axi.yaml16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so
17 called AXI Main Interconnect) routing IO requests from one block to
22 (Errors Handler Block) embedded on top of the DW AXI Interconnect and
36 - description: Synopsys DesignWare AXI Interconnect QoS registers
45 '#interconnect-cells':
57 - description: Main Interconnect uplink reference clock
65 - description: Main Interconnect reset line
93 #interconnect-cells = <1>;
/Linux-v5.10/drivers/interconnect/qcom/
DKconfig3 bool "Qualcomm Network-on-Chip interconnect drivers"
6 Support for Qualcomm's Network-on-Chip interconnect hardware.
12 tristate "Qualcomm MSM8916 interconnect driver"
21 tristate "Qualcomm MSM8974 interconnect driver"
30 tristate "Qualcomm OSM L3 interconnect driver"
33 Say y here to support the Operating State Manager (OSM) interconnect
37 tristate "Qualcomm QCS404 interconnect driver"
49 tristate "Qualcomm SC7180 interconnect driver"
59 tristate "Qualcomm SDM845 interconnect driver"
69 tristate "Qualcomm SM8150 interconnect driver"
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/Linux-v5.10/drivers/interconnect/imx/
DMakefile1 imx-interconnect-objs := imx.o
2 imx8mm-interconnect-objs := imx8mm.o
3 imx8mq-interconnect-objs := imx8mq.o
4 imx8mn-interconnect-objs := imx8mn.o
6 obj-$(CONFIG_INTERCONNECT_IMX) += imx-interconnect.o
7 obj-$(CONFIG_INTERCONNECT_IMX8MM) += imx8mm-interconnect.o
8 obj-$(CONFIG_INTERCONNECT_IMX8MQ) += imx8mq-interconnect.o
9 obj-$(CONFIG_INTERCONNECT_IMX8MN) += imx8mn-interconnect.o
DKconfig2 tristate "i.MX interconnect drivers"
5 Generic interconnect drivers for i.MX SOCs
8 tristate "i.MX8MM interconnect driver"
12 tristate "i.MX8MN interconnect driver"
16 tristate "i.MX8MQ interconnect driver"
/Linux-v5.10/drivers/interconnect/
Dcore.c3 * Interconnect framework core driver
13 #include <linux/interconnect.h>
14 #include <linux/interconnect-provider.h>
322 * @spec: OF phandle args to map into an interconnect node.
326 * interconnect providers that have one device tree node and provide
327 * multiple interconnect nodes. A single cell is used as an index into
347 * of_icc_get_from_provider() - Look-up interconnect node
350 * Looks for interconnect provider under the node specified by @spec and if
425 * @idx: interconnect path index
430 * If the interconnect API is disabled, NULL is returned and the consumer
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DKconfig2 menuconfig INTERCONNECT config
3 bool "On-Chip Interconnect management support"
12 if INTERCONNECT
14 source "drivers/interconnect/imx/Kconfig"
15 source "drivers/interconnect/qcom/Kconfig"
/Linux-v5.10/include/linux/
Dinterconnect-provider.h10 #include <linux/interconnect.h>
29 * struct icc_onecell_data - driver data for onecell interconnect providers
43 * struct icc_provider - interconnect provider (controller) entity that might
44 * provide multiple interconnect controls
46 * @provider_list: list of the registered interconnect providers
47 * @nodes: internal list of the interconnect provider nodes
55 * @dev: the device this interconnect provider belongs to
77 * struct icc_node - entity that is part of the interconnect topology
82 * @num_links: number of links to other interconnect nodes
83 * @provider: points to the interconnect provider of this node
/Linux-v5.10/Documentation/devicetree/bindings/arm/
Dcci.txt2 ARM CCI cache coherent interconnect binding description
6 cache coherent interconnect (CCI) that is capable of monitoring bus
14 * CCI interconnect node
16 Description: Describes a CCI cache coherent Interconnect component
20 through the CCI interconnect is the same as the one seen from the
51 CCI interconnect node can define the following child nodes:
56 Parent node must be CCI interconnect node.
85 Parent node must be CCI interconnect node.
124 * CCI interconnect bus masters
129 A CCI interconnect bus master node must contain the following
/Linux-v5.10/drivers/bus/
DKconfig21 interconnect for ARM platforms.
48 Interconnect. In case of any APB protocol collisions, slave device
64 Interconnect (so called AXI Main Interconnect) routing IO requests
67 means of an embedded on top of the interconnect errors handler
68 block (EHB). AXI Interconnect QoS arbitration tuning is currently
119 tristate "OMAP INTERCONNECT DRIVER"
123 Driver to enable OMAP interconnect error handling driver.
202 bool "TI sysc interconnect target module driver"
205 Generic driver for Texas Instruments interconnect target module
/Linux-v5.10/Documentation/devicetree/bindings/mmc/
Dsdhci-msm.txt58 * Following bus parameters are required for interconnect bandwidth scaling:
59 - interconnects: Pairs of phandles and interconnect provider specifier
61 the interconnect path.
63 - interconnect-names: For sdhc, we have two main paths.
66 For Data interconnect path the name supposed to be
67 is "sdhc-ddr" and for config interconnect path it is
70 interconnect/ for more details.
91 interconnect-names = "sdhc-ddr","cpu-sdhc";
/Linux-v5.10/Documentation/devicetree/bindings/arm/omap/
Dl4.txt1 L4 interconnect bindings
3 These bindings describe the OMAP SoCs L4 interconnect bus.
19 - reg : registers link agent and interconnect agent and access protection
21 interconnect agent instances, "ap" for access if it exists
25 l4: interconnect@48000000 {
/Linux-v5.10/Documentation/devicetree/bindings/arm/sunxi/
Dallwinner,sun4i-a10-mbus.yaml20 the interconnects and interconnect-names properties set to the MBUS
21 controller and with "dma-mem" as the interconnect name.
24 "#interconnect-cells":
50 - "#interconnect-cells"
69 #interconnect-cells = <1>;
/Linux-v5.10/Documentation/devicetree/bindings/net/
Dqcom,ipa.yaml23 See also soc/qcom/qcom,smp2p.txt and interconnect/interconnect.txt. See
85 - description: Interconnect path between IPA and main memory
86 - description: Interconnect path between IPA and internal memory
87 - description: Interconnect path between IPA and the AP subsystem
89 interconnect-names:
153 #include <dt-bindings/interconnect/qcom,sdm845.h>
198 interconnect-names = "memory",
/Linux-v5.10/Documentation/devicetree/bindings/display/msm/
Ddpu.txt31 - interconnects : interconnect path specifier for MDSS according to
32 Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be
34 - interconnect-names : MDSS will have 2 port names to differentiate between the
35 2 interconnect paths defined with interconnect specifier.
97 interconnect-names = "mdp0-mem", "mdp1-mem";
Dgpu.txt25 - interconnects: optional phandle to an interconnect provider. See
26 ../interconnect/interconnect.txt for details. Some A3xx and all A4xx platforms
28 - interconnect-names: The names of the interconnect paths that correspond to the
113 interconnect-names = "gfx-mem";
/Linux-v5.10/include/linux/platform_data/
Dti-sysc.h83 * struct sysc_capabilities - capabilities for an interconnect target module
97 * struct sysc_config - configuration for an interconnect target module
124 * @module_pa: physical address of the interconnect target module
125 * @module_size: size of the interconnect target module
128 * @cap: interconnect target module capabilities
129 * @cfg: interconnect target module configuration

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