Lines Matching full:interconnect

1 Texas Instruments sysc interconnect target module wrapper binding
3 Texas Instruments SoCs can have a generic interconnect target module
5 interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc
8 of the interconnect.
10 Each interconnect target module can have one or more devices connected to
11 it. There is a set of control registers for managing interconnect target
12 module clocks, idle modes and interconnect level resets for the module.
15 space of the first child device IP block managed by the interconnect
43 - reg		shall have register areas implemented for the interconnect
47 		interconnect target module in question such as
50 - ranges	shall contain the interconnect target module IO range
52 		by the interconnect target module, the ranges may include
60 		Manual (TRM) for the interconnect target module
62 - ti,sysc-midle	list of master idle modes supported by the interconnect
66 - ti,sysc-sidle	list of slave idle modes supported by the interconnect
80 		typically available for all interconnect targets on TI SoCs
85 		depending on the SoC and the interconnect target module,
86 		some interconnect target modules also need additional
91 - ti,hwmods	optional TI interconnect module name to use legacy
94 - ti,no-reset-on-init	interconnect target module should not be reset at init
96 - ti,no-idle-on-init	interconnect target module should not be idled at init
98 - ti,no-idle		interconnect target module should not be idled
100 Example: Single instance of MUSB controller on omap4 using interconnect ranges
139 instance as children of a single interconnect target module.