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/Linux-v5.15/Documentation/devicetree/bindings/i3c/
Di3c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
11 - Miquel Raynal <miquel.raynal@bootlin.com>
15 and a set of child nodes for each I2C or I3C slave on the bus. Each of them
20 pattern: "^i3c-master@[0-9a-f]+$"
22 "#address-cells":
25 Each I2C device connected to the bus should be described in a subnode.
35 this I3C device has a static I2C address and we want to assign it a
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Dcdns,i3c-master.txt5 --------------------
6 - compatible: shall be "cdns,i3c-master"
7 - clocks: shall reference the pclk and sysclk
8 - clock-names: shall contain "pclk" and "sysclk"
9 - interrupts: the interrupt line connected to this I3C master
10 - reg: I3C master registers
15 - #address-cells: shall be set to 1
16 - #size-cells: shall be set to 0
21 - i2c-scl-hz
22 - i3c-scl-hz
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Dsnps,dw-i3c-master.txt5 --------------------
6 - compatible: shall be "snps,dw-i3c-master-1.00a"
7 - clocks: shall reference the core_clk
8 - interrupts: the interrupt line connected to this I3C master
9 - reg: Offset and length of I3C master registers
14 - #address-cells: shall be set to 3
15 - #size-cells: shall be set to 0
20 - i2c-scl-hz
21 - i3c-scl-hz
28 i3c-master@2000 {
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/Linux-v5.15/Documentation/devicetree/bindings/i2c/
Di2c.txt1 Generic device tree bindings for I2C busses
4 This document describes generic bindings which can be used to describe I2C
8 -----------------------------
10 - #address-cells - should be <1>. Read more about addresses below.
11 - #size-cells - should be <0>.
12 - compatible - name of I2C bus controller
17 The cells properties above define that an address of children of an I2C bus
21 -----------------------------
26 - clock-frequency
27 frequency of bus clock in Hz.
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Dst,stm32-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/st,stm32-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: I2C controller embedded in STMicroelectronics STM32 I2C platform
10 - Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
19 - st,stm32f7-i2c
20 - st,stm32mp15-i2c
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Di2c-rk3x.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-rk3x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3xxx I2C controller
10 This driver interfaces with the native I2C controller present in Rockchip
14 - $ref: /schemas/i2c/i2c-controller.yaml#
17 - Heiko Stuebner <heiko@sntech.de>
23 - const: rockchip,rv1108-i2c
24 - const: rockchip,rk3066-i2c
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Drenesas,rcar-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/renesas,rcar-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car I2C Controller
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
15 - items:
16 - enum:
17 - renesas,i2c-r8a7778 # R-Car M1A
18 - renesas,i2c-r8a7779 # R-Car H1
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Di2c-st.txt1 ST SSC binding, for I2C mode operation
4 - compatible : Must be "st,comms-ssc-i2c" or "st,comms-ssc4-i2c"
5 - reg : Offset and length of the register set for the device
6 - interrupts : the interrupt specifier
7 - clock-names: Must contain "ssc".
8 - clocks: Must contain an entry for each name in clock-names. See the common
10 - A pinctrl state named "default" must be defined to set pins in mode of
11 operation for I2C transfer.
14 - clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
17 - st,i2c-min-scl-pulse-width-us : The minimum valid SCL pulse width that is
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Di2c-s3c2410.txt1 * Samsung's I2C controller
3 The Samsung's I2C controller is used to interface with I2C devices.
6 - compatible: value should be either of the following.
7 (a) "samsung, s3c2410-i2c", for i2c compatible with s3c2410 i2c.
8 (b) "samsung, s3c2440-i2c", for i2c compatible with s3c2440 i2c.
9 (c) "samsung, s3c2440-hdmiphy-i2c", for s3c2440-like i2c used
11 (d) "samsung, exynos5-sata-phy-i2c", for s3c2440-like i2c used as
13 - reg: physical base address of the controller and length of memory mapped
15 - interrupts: interrupt number to the cpu.
16 - samsung,i2c-sda-delay: Delay (in ns) applied to data line (SDA) edges.
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Di2c-at91.txt1 I2C for Atmel platforms
4 - compatible : Must be one of:
5 "atmel,at91rm9200-i2c",
6 "atmel,at91sam9261-i2c",
7 "atmel,at91sam9260-i2c",
8 "atmel,at91sam9g20-i2c",
9 "atmel,at91sam9g10-i2c",
10 "atmel,at91sam9x5-i2c",
11 "atmel,sama5d4-i2c",
12 "atmel,sama5d2-i2c",
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Dsnps,designware-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare APB I2C Controller
10 - Jarkko Nikula <jarkko.nikula@linux.intel.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
19 const: mscc,ocelot-i2c
28 - description: Generic Synopsys DesignWare I2C controller
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Di2c-mt65xx.txt1 * MediaTek's I2C controller
3 The MediaTek's I2C controller is used to interface with I2C devices.
6 - compatible: value should be either of the following.
7 "mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for MediaTek MT2701
8 "mediatek,mt2712-i2c": for MediaTek MT2712
9 "mediatek,mt6577-i2c": for MediaTek MT6577
10 "mediatek,mt6589-i2c": for MediaTek MT6589
11 "mediatek,mt6797-i2c", "mediatek,mt6577-i2c": for MediaTek MT6797
12 "mediatek,mt7622-i2c": for MediaTek MT7622
13 "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
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/Linux-v5.15/drivers/i2c/busses/
Di2c-acorn.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM IOC/IOMD i2c driver.
7 * On Acorn machines, the following i2c devices are on the bus:
8 * - PCF8583 real time clock & static RAM
11 #include <linux/i2c.h>
12 #include <linux/i2c-algo-bit.h>
19 #define SCL 0x02 macro
23 * We must preserve all non-i2c output bits in IOC_CONTROL.
24 * Note also that we need to preserve the value of SCL and
32 u_int ioc_control = ioc_readb(IOC_CONTROL) & ~(SCL | SDA); in ioc_setscl()
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Di2c-versatile.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-versatile.c
10 #include <linux/i2c.h>
11 #include <linux/i2c-algo-bit.h>
20 #define SCL (1 << 0) macro
31 struct i2c_versatile *i2c = data; in i2c_versatile_setsda() local
33 writel(SDA, i2c->base + (state ? I2C_CONTROLS : I2C_CONTROLC)); in i2c_versatile_setsda()
38 struct i2c_versatile *i2c = data; in i2c_versatile_setscl() local
40 writel(SCL, i2c->base + (state ? I2C_CONTROLS : I2C_CONTROLC)); in i2c_versatile_setscl()
45 struct i2c_versatile *i2c = data; in i2c_versatile_getsda() local
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Di2c-gpio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Bitbanging I2C bus driver using the GPIO API
11 #include <linux/i2c-algo-bit.h>
12 #include <linux/i2c.h>
17 #include <linux/platform_data/i2c-gpio.h>
23 struct gpio_desc *scl; member
44 gpiod_set_value_cansleep(priv->sda, state); in i2c_gpio_setsda_val()
48 * Toggle SCL by changing the output value of the pin. This is used
49 * for pins that are configured as open drain and for output-only
50 * pins. The latter case will break the i2c protocol, but it will
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Di2c-qcom-geni.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
6 #include <linux/dma-mapping.h>
8 #include <linux/i2c.h>
15 #include <linux/qcom-geni-se.h>
26 /* M_CMD OP codes for I2C */
33 /* M_CMD params for I2C */
44 /* I2C SCL COUNTER fields */
71 #define ABORT_TIMEOUT HZ
72 #define XFER_TIMEOUT HZ
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Di2c-stm32f7.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for STMicroelectronics STM32F7 I2C controller
5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
14 * This driver is based on i2c-stm32f4.c
20 #include <linux/i2c.h>
21 #include <linux/i2c-smbus.h>
38 #include "i2c-stm32.h"
40 /* STM32F7 I2C registers */
52 /* STM32F7 I2C control 1 */
83 /* STM32F7 I2C control 2 */
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Di2c-omap.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TI OMAP I2C master mode driver
7 * Copyright (C) 2004 - 2007 Texas Instruments.
20 #include <linux/i2c.h>
30 #include <linux/platform_data/i2c-omap.h>
34 /* I2C controller revisions */
37 /* I2C controller revisions present on specific hardware */
80 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
89 /* I2C Status Register (OMAP_I2C_STAT): */
103 /* I2C WE wakeup enable register */
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Di2c-designware-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare I2C adapter driver.
5 * Based on the TI DAVINCI I2C adapter driver.
18 #include <linux/i2c.h>
29 #include "i2c-designware-core.h"
59 "incorrect slave-transmitter mode configuration",
66 *val = readl_relaxed(dev->base + reg); in dw_reg_read()
75 writel_relaxed(val, dev->base + reg); in dw_reg_write()
84 *val = swab32(readl_relaxed(dev->base + reg)); in dw_reg_read_swab()
93 writel_relaxed(swab32(val), dev->base + reg); in dw_reg_write_swab()
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Di2c-davinci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TI DAVINCI I2C adapter driver.
10 * ----------------------------------------------------------------------------
12 * ----------------------------------------------------------------------------
17 #include <linux/i2c.h>
29 #include <linux/platform_data/i2c-davinci.h>
32 /* ----- global defines ----------------------------------------------- */
34 #define DAVINCI_I2C_TIMEOUT (1*HZ)
94 /* set SDA and SCL as GPIO */
97 /* set SCL as output when used as GPIO*/
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/Linux-v5.15/arch/arm/boot/dts/
Drk3288-veyron.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
14 stdout-path = "serial2:115200n8";
27 power_button: power-button {
28 compatible = "gpio-keys";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pwr_key_l>;
36 debounce-interval = <100>;
37 wakeup-source;
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/Linux-v5.15/drivers/media/pci/ivtv/
Divtv-i2c.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 I2C functions
4 Copyright (C) 2003-2004 Kevin Thayer <nufan_wfk at yahoo.com>
5 Copyright (C) 2005-2007 Hans Verkuil <hverkuil@xs4all.nl>
10 This file includes an i2c implementation that was reverse engineered
11 from the Hauppauge windows driver. Older ivtv versions used i2c-algo-bit,
13 CPU on the PVR-150 which handles IR functions (occasional inability to
14 communicate with the chip until it was reset) and also with the i2c
17 The implementation is very similar to i2c-algo-bit, but there are enough
19 employed by i2c-algo-bit is to use udelay() to implement the timing
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/Linux-v5.15/drivers/net/can/sja1000/
Dpeak_pci.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2012 Stephane Grosjean <s.grosjean@peak-system.com>
8 * Copyright (C) 2001-2006 PEAK System-Technik GmbH
18 #include <linux/i2c.h>
19 #include <linux/i2c-algo-bit.h>
25 MODULE_AUTHOR("Stephane Grosjean <s.grosjean@peak-system.com>");
26 MODULE_DESCRIPTION("Socket-CAN driver for PEAK PCAN PCI family cards");
62 #define PEAK_PC_104P_DEVICE_ID 0x0006 /* PCAN-PC/104+ cards */
63 #define PEAK_PCI_104E_DEVICE_ID 0x0007 /* PCAN-PCI/104 Express cards */
65 #define PEAK_PCIE_OEM_ID 0x0009 /* PCAN-PCI Express OEM */
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/Linux-v5.15/include/linux/
Di2c.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * i2c.h - definitions for the Linux i2c bus interface
4 * Copyright (C) 1995-2000 Simon G. Vogl
5 * Copyright (C) 2013-2019 Wolfram Sang <wsa@kernel.org>
23 #include <uapi/linux/i2c.h>
29 /* --- General options ------------------------------------------------ */
43 /* I2C Frequency Modes */
69 * i2c_master_recv - issue a single I2C message in master receive mode
83 * i2c_master_recv_dmasafe - issue a single I2C message in master receive mode
99 * i2c_master_send - issue a single I2C message in master transmit mode
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/Linux-v5.15/Documentation/ABI/testing/
Dsysfs-bus-i3c1 What: /sys/bus/i3c/devices/i3c-<bus-id>
3 Contact: linux-i3c@vger.kernel.org
5 An I3C bus. This directory will contain one sub-directory per
8 What: /sys/bus/i3c/devices/i3c-<bus-id>/current_master
10 Contact: linux-i3c@vger.kernel.org
12 Expose the master that owns the bus (<bus-id>-<master-pid>) at
17 What: /sys/bus/i3c/devices/i3c-<bus-id>/mode
19 Contact: linux-i3c@vger.kernel.org
21 I3C bus mode. Can be "pure", "mixed-fast" or "mixed-slow". See
25 What: /sys/bus/i3c/devices/i3c-<bus-id>/i3c_scl_frequency
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