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/Linux-v5.15/drivers/net/can/usb/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "CAN USB interfaces"
3 depends on USB
12 tristate "EMS CPC-USB/ARM7 CAN/USB interface"
14 This driver is for the one channel CPC-USB/ARM7 CAN/USB interface
15 from EMS Dr. Thomas Wuensche (http://www.ems-wuensche.de).
18 tristate "ESD USB/2 CAN/USB interface"
20 This driver supports the CAN-USB/2 interface
24 tristate "ETAS ES58X CAN/USB interfaces"
37 candleLight USB CAN interfaces USB/CAN devices
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/phy/
Dnvidia,tegra20-usb-phy.txt1 Tegra SOC USB PHY
3 The device node for Tegra SOC USB PHY:
6 - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy".
7 For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain
8 "nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is
10 - reg : Defines the following set of registers, in the order listed:
11 - The PHY's own register set.
13 - The register set of the PHY containing the UTMI pad control registers.
14 Present if-and-only-if phy_type == utmi.
15 - phy_type : Should be one of "utmi", "ulpi" or "hsic".
[all …]
Drcar-gen2-phy.txt1 * Renesas R-Car generation 2 USB PHY
3 This file provides information on what the device node for the R-Car generation
4 2 USB PHY contains.
7 - compatible: "renesas,usb-phy-r8a7742" if the device is a part of R8A7742 SoC.
8 "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC.
9 "renesas,usb-phy-r8a7744" if the device is a part of R8A7744 SoC.
10 "renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC.
11 "renesas,usb-phy-r8a77470" if the device is a part of R8A77470 SoC.
12 "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
13 "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
[all …]
Dsocionext,uniphier-usb3hs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-usb3-hsphy
22 - socionext,uniphier-pxs2-usb3-hsphy
[all …]
/Linux-v5.15/drivers/phy/qualcomm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 tristate "Atheros AR71XX/9XXX USB PHY driver"
8 default y if USB_EHCI_HCD_PLATFORM || USB_OHCI_HCD_PLATFORM
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
22 tristate "Qualcomm IPQ4019 USB PHY driver"
26 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
49 with controllers such as PCIe, UFS, and USB on Qualcomm chips.
57 Enable this to support the HighSpeed QUSB2 PHY transceiver for USB
58 controllers on Qualcomm chips. This driver supports the high-speed
60 USB IPs on MSM SOCs.
[all …]
Dphy-qcom-snps-femto-v2.c1 // SPDX-License-Identifier: GPL-2.0
63 "vdda-pll", "vdda33", "vdda18",
69 * struct qcom_snps_hsphy - snps hs phy attributes
72 * @base: iomapped memory space for snps hs phy
79 * @phy_initialized: if PHY has been initialized correctly
111 dev_dbg(&hsphy->phy->dev, "Suspend QCOM SNPS PHY\n"); in qcom_snps_hsphy_suspend()
113 if (hsphy->mode == PHY_MODE_USB_HOST) { in qcom_snps_hsphy_suspend()
114 /* Enable auto-resume to meet remote wakeup timing */ in qcom_snps_hsphy_suspend()
115 qcom_snps_hsphy_write_mask(hsphy->base, in qcom_snps_hsphy_suspend()
120 qcom_snps_hsphy_write_mask(hsphy->base, in qcom_snps_hsphy_suspend()
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/Linux-v5.15/Documentation/devicetree/bindings/clock/
Drenesas,rcar-usb2-clock-sel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/clock/renesas,rcar-usb2-clock-sel.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Renesas R-Car USB 2.0 clock selector
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
13 If you connect an external clock to the USB_EXTAL pin only, you should set
15 If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module
19 Case 1: An external clock connects to R-Car SoC
20 +----------+ +--- R-Car ---------------------+
[all …]
/Linux-v5.15/drivers/usb/host/
Dehci-xilinx-of.c1 // SPDX-License-Identifier: GPL-2.0+
3 * EHCI HCD (Host Controller Driver) for USB.
9 * Based on "ehci-ppc-of.c" by Valentine Barshak <vbarshak@ru.mvista.com>
10 * and "ehci-ppc-soc.c" by Stefan Roese <sr@denx.de>
11 * and "ohci-ppc-of.c" by Sylvain Munaut <tnt@246tNt.com>
23 * ehci_xilinx_port_handed_over - hand the port out if failed to enable it
27 * This function is used as a place to tell the user that the Xilinx USB host
28 * controller does support LS devices. And in an HS only configuration, it
34 * the USB bus. In those cases, the messages printed here are not helpful.
38 dev_warn(hcd->self.controller, "port %d cannot be enabled\n", portnum); in ehci_xilinx_port_handed_over()
[all …]
/Linux-v5.15/drivers/usb/cdns3/
Dcdns3-gadget.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2018-2019 Cadence.
6 * Copyright (C) 2017-2018 NXP
14 #include <linux/usb/gadget.h>
15 #include <linux/dma-direction.h>
18 * USBSS-DEV register interface.
23 * struct cdns3_usb_regs - device controller registers.
29 * @usb_ien: USB Interrupt Enable.
30 * @usb_ists: USB Interrupt Status.
53 * @buf_addr: Address for On-chip Buffer operations.
[all …]
DKconfig2 tristate "Cadence USB Support"
3 depends on USB_SUPPORT && (USB || USB_GADGET) && HAS_DMA
4 select USB_XHCI_PLATFORM if USB_XHCI_HCD
7 Say Y here if your system has a Cadence USBSS or USBSSP
8 dual-role controller.
9 It supports: dual-role switch, Host-only, and Peripheral-only.
14 if USB_CDNS_SUPPORT
17 tristate "Cadence USB3 Dual-Role Controller"
20 Say Y here if your system has a Cadence USB3 dual-role controller.
21 It supports: dual-role switch, Host-only, and Peripheral-only.
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/usb/
Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtu3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: "usb-drd.yaml"
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
[all …]
Dqcom,dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
10 - Manu Gautam <mgautam@codeaurora.org>
15 - enum:
16 - qcom,msm8996-dwc3
17 - qcom,msm8998-dwc3
18 - qcom,sc7180-dwc3
[all …]
Dci-hdrc-usb2.txt1 * USB2 ChipIdea USB controller for ci13xxx
4 - compatible: should be one of:
5 "fsl,imx23-usb"
6 "fsl,imx27-usb"
7 "fsl,imx28-usb"
8 "fsl,imx6q-usb"
9 "fsl,imx6sl-usb"
10 "fsl,imx6sx-usb"
11 "fsl,imx6ul-usb"
12 "fsl,imx7d-usb"
[all …]
Dsnps,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
27 $ref: usb.yaml#
[all …]
Dehci-omap.txt1 OMAP HS USB EHCI controller
3 This device is usually the child of the omap-usb-host
4 Documentation/devicetree/bindings/mfd/omap-usb-host.txt
8 - compatible: should be "ti,ehci-omap"
9 - reg: should contain one register range i.e. start and length
10 - interrupts: description of the interrupt line
14 - phys: list of phandles to PHY nodes.
15 This property is required if at least one of the ports are in
19 Documentation/devicetree/bindings/mfd/omap-usb-host.txt
24 compatible = "ti,ehci-omap";
Ddwc3-xilinx.txt1 Xilinx SuperSpeed DWC3 USB SoC controller
4 - compatible: May contain "xlnx,zynqmp-dwc3" or "xlnx,versal-dwc3"
5 - reg: Base address and length of the register control block
6 - clocks: A list of phandles for the clocks listed in clock-names
7 - clock-names: Should contain the following:
9 operation and >= 60MHz for HS operation
12 - resets: A list of phandles for resets listed in reset-names
13 - reset-names:
14 "usb_crst" USB core reset
15 "usb_hibrst" USB hibernation reset
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/connector/
Dusb-connector.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/connector/usb-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: USB Connector
10 - Rob Herring <robh@kernel.org>
13 A USB connector node represents a physical USB connector. It should be a child
14 of a USB interface controller or a separate node when it is attached to both
15 MUX and USB interface controller.
20 - enum:
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/mfd/
Domap-usb-host.txt1 OMAP HS USB Host
5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
16 from 1 to 3. If the port mode is not specified, that port is treated
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
[all …]
/Linux-v5.15/drivers/usb/gadget/
Dconfig.c1 // SPDX-License-Identifier: GPL-2.0+
3 * usb/gadget/config.c -- simplify building config descriptors
16 #include <linux/usb/ch9.h>
17 #include <linux/usb/gadget.h>
18 #include <linux/usb/composite.h>
19 #include <linux/usb/otg.h>
22 * usb_descriptor_fillbuf - fill buffer with descriptors
28 * negative error code if they can't all be copied. Useful when
39 if (!src) in usb_descriptor_fillbuf()
40 return -EINVAL; in usb_descriptor_fillbuf()
[all …]
/Linux-v5.15/drivers/usb/dwc2/
Dgadget.c1 // SPDX-License-Identifier: GPL-2.0
11 * S3C USB2.0 High-speed / OtG driver
19 #include <linux/dma-mapping.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29 #include <linux/usb/phy.h>
30 #include <linux/usb/composite.h>
65 if (dir_in) in index_to_ep()
66 return hsotg->eps_in[ep_index]; in index_to_ep()
68 return hsotg->eps_out[ep_index]; in index_to_ep()
[all …]
Dpci.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * pci.c - DesignWare HS OTG Controller PCI driver
5 * Copyright (C) 2004-2013 Synopsys, Inc.
16 * 3. The names of the above-listed copyright holders may not be used
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
50 #include <linux/usb.h>
52 #include <linux/usb/hcd.h>
53 #include <linux/usb/ch11.h>
55 #include <linux/usb/usb_phy_generic.h>
59 static const char dwc2_driver_name[] = "dwc2-pci";
[all …]
/Linux-v5.15/drivers/net/can/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 This driver can also be built as a module. If so, the module
28 This driver can also be built as a module. If so, the module
32 tristate "Serial / USB serial CAN Adaptors (slcan)"
36 via serial lines or via USB-to-serial adapters using the LAWICEL
40 driver should work with the (serial/USB) CAN hardware from:
44 slcand) can be found in the can-utils at the linux-can project, see
45 https://github.com/linux-can/can-utils for details.
49 also be built as a module. If so, the module will be called slcan.
57 If unsure, say Y.
[all …]
/Linux-v5.15/drivers/usb/gadget/udc/
Damd5536udc_pci.c1 // SPDX-License-Identifier: GPL-2.0+
3 * amd5536udc_pci.c -- AMD 5536 UDC high/full speed USB device controller
5 * Copyright (C) 2005-2007 AMD (https://www.amd.com)
11 * It is a USB Highspeed DMA capable USB device controller. Beside ep0 it
18 * UDC DMA requires 32-bit aligned buffers so DMA with gadget ether does not
26 * Synopsys device controller IP (different than HS OTG IP) in UDCs
32 #define UDC_MOD_DESCRIPTION "AMD 5536 UDC - USB Device Controller"
52 static const char name[] = "amd5536udc-pci";
61 usb_del_gadget_udc(&udc->gadget); in udc_pci_remove()
63 if (WARN_ON(dev->driver)) in udc_pci_remove()
[all …]
/Linux-v5.15/arch/mips/cavium-octeon/
Docteon-usb.c4 * Copyright (C) 2010-2017 Cavium Networks
20 /* USB Control Register */
24 /* 1 = BIST and set all USB RAMs to 0x0, 0 = BIST */
37 /* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
39 /* Spread-spectrum clock modulation range:
40 * 0x0 = -4980 ppm downspread
41 * 0x1 = -4492 ppm downspread
42 * 0x2 = -4003 ppm downspread
43 * 0x3 - 0x7 = Reserved
46 /* Enable non-standard oscillator frequencies:
[all …]
/Linux-v5.15/drivers/staging/octeon-usb/
Docteon-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
41 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
106 * configuration parameters. The AHB is the processor interface to the O2P USB
110 * The application must program this register as part of the O2P USB core
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
131 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
[all …]

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