4  * Copyright (C) 2010-2017 Cavium Networks
20 /* USB Control Register */
24 	/* 1 = BIST and set all USB RAMs to 0x0, 0 = BIST */
37 	/* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
39 	/* Spread-spectrum clock modulation range:
40 	 *	0x0 = -4980 ppm downspread
41 	 *	0x1 = -4492 ppm downspread
42 	 *	0x2 = -4003 ppm downspread
43 	 *	0x3 - 0x7 = Reserved
46 	/* Enable non-standard oscillator frequencies:
47 	 *	[55:53] = modules -1
51 	/* Reference clock multiplier for non-standard frequencies:
52 	 *	0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
53 	 *	0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
54 	 *	0x32 =  50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
64 	 *	If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal
65 	 *	If REF_CLK_SEL = 0x2 or 0x3, then:
123 	/* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */
147 	/* HS jitter adjustment */
151 	/* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */
156 	 *	0x0 = Overcurrent indication from off-chip is active-low
157 	 *	0x1 = Overcurrent indication from off-chip is active-high
163 	 *	0x0 = Port power to off-chip is active-low
164 	 *	0x1 = Port power to off-chip is active-high
177 	/* Out-of-bound UAHC register access: 0 = read, 1 = write */
181 	/* SRCID error log for out-of-bound UAHC register access:
183 	 *	[57] = Request source: 0 = core, 1 = NCB-device
184 	 *	[56:51] = Core/NCB-device number, [56] always 0 for NCB devices
235 	struct device_node *node = dev->of_node;  in dwc3_octeon_config_power()
238 	if (of_find_property(node, "power", &len) != NULL) {  in dwc3_octeon_config_power()
239 		if (len == 12) {  in dwc3_octeon_config_power()
243 		} else if (len == 8) {  in dwc3_octeon_config_power()
249 			return -EINVAL;  in dwc3_octeon_config_power()
251 		if ((OCTEON_IS_MODEL(OCTEON_CN73XX) ||  in dwc3_octeon_config_power()
258 		} else if (gpio <= 15) {  in dwc3_octeon_config_power()
270 		/* Enable XHCI power control and set if active high or low. */  in dwc3_octeon_config_power()
276 		/* Disable XHCI power control and set if active high. */  in dwc3_octeon_config_power()
297 	if (dev->of_node) {  in dwc3_octeon_clocks_start()
301 		i = of_property_read_u32(dev->of_node,  in dwc3_octeon_clocks_start()
302 					 "refclk-frequency", &clock_rate);  in dwc3_octeon_clocks_start()
303 		if (i) {  in dwc3_octeon_clocks_start()
304 			pr_err("No UCTL \"refclk-frequency\"\n");  in dwc3_octeon_clocks_start()
305 			return -EINVAL;  in dwc3_octeon_clocks_start()
307 		i = of_property_read_string(dev->of_node,  in dwc3_octeon_clocks_start()
308 					    "refclk-type-ss", &ss_clock_type);  in dwc3_octeon_clocks_start()
309 		if (i) {  in dwc3_octeon_clocks_start()
310 			pr_err("No UCTL \"refclk-type-ss\"\n");  in dwc3_octeon_clocks_start()
311 			return -EINVAL;  in dwc3_octeon_clocks_start()
313 		i = of_property_read_string(dev->of_node,  in dwc3_octeon_clocks_start()
314 					    "refclk-type-hs", &hs_clock_type);  in dwc3_octeon_clocks_start()
315 		if (i) {  in dwc3_octeon_clocks_start()
316 			pr_err("No UCTL \"refclk-type-hs\"\n");  in dwc3_octeon_clocks_start()
317 			return -EINVAL;  in dwc3_octeon_clocks_start()
319 		if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) {  in dwc3_octeon_clocks_start()
320 			if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0)  in dwc3_octeon_clocks_start()
322 			else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)  in dwc3_octeon_clocks_start()
325 				pr_err("Invalid HS clock type %s, using  pll_ref_clk instead\n",  in dwc3_octeon_clocks_start()
327 		} else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) {  in dwc3_octeon_clocks_start()
328 			if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0)  in dwc3_octeon_clocks_start()
330 			else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)  in dwc3_octeon_clocks_start()
333 				pr_err("Invalid HS clock type %s, using  pll_ref_clk instead\n",  in dwc3_octeon_clocks_start()
341 		if ((ref_clk_sel == 0 || ref_clk_sel == 1) &&  in dwc3_octeon_clocks_start()
347 		pr_err("No USB UCTL device node\n");  in dwc3_octeon_clocks_start()
348 		return -EINVAL;  in dwc3_octeon_clocks_start()
356 	/* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */  in dwc3_octeon_clocks_start()
373 		if (h_clk_rate <= OCTEON_MAX_H_CLK_RATE &&  in dwc3_octeon_clocks_start()
382 	if ((div != uctl_ctl.s.h_clkdiv_sel) || (!uctl_ctl.s.h_clk_en)) {  in dwc3_octeon_clocks_start()
384 			return -EINVAL;  in dwc3_octeon_clocks_start()
404 		if (ref_clk_sel < 2)  in dwc3_octeon_clocks_start()
416 	/* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */  in dwc3_octeon_clocks_start()
429 	/* Step 7: Wait 10 controller-clock cycles to take effect. */  in dwc3_octeon_clocks_start()
437 	/* Step 8b: Wait 10 controller-clock cycles. */  in dwc3_octeon_clocks_start()
440 	/* Steo 8c: Setup power-power control. */  in dwc3_octeon_clocks_start()
441 	if (dwc3_octeon_config_power(dev, base)) {  in dwc3_octeon_clocks_start()
443 		return -EINVAL;  in dwc3_octeon_clocks_start()
451 	/* Step 8e: Wait 10 controller-clock cycles. */  in dwc3_octeon_clocks_start()
498 	const char compat_node_name[] = "cavium,octeon-7130-usb-uctl";  in dwc3_octeon_device_init()
506 	 * in the device tree. Two USB and a SATA, which we ignore.  in dwc3_octeon_device_init()
511 		if (!node)  in dwc3_octeon_device_init()
512 			return -ENODEV;  in dwc3_octeon_device_init()
514 		if (of_device_is_compatible(node, compat_node_name)) {  in dwc3_octeon_device_init()
516 			if (!pdev)  in dwc3_octeon_device_init()
517 				return -ENODEV;  in dwc3_octeon_device_init()
526 			if (IS_ERR(base)) {  in dwc3_octeon_device_init()
527 				put_device(&pdev->dev);  in dwc3_octeon_device_init()
532 			dwc3_octeon_clocks_start(&pdev->dev, (u64)base);  in dwc3_octeon_device_init()
535 			dev_info(&pdev->dev, "clocks initialized.\n");  in dwc3_octeon_device_init()
537 			devm_iounmap(&pdev->dev, base);  in dwc3_octeon_device_init()
538 			devm_release_mem_region(&pdev->dev, res->start,  in dwc3_octeon_device_init()
549 MODULE_DESCRIPTION("USB driver for OCTEON III SoC");