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/Linux-v6.1/drivers/gpu/drm/sun4i/
Dsun8i_hdmi_phy.c1 // SPDX-License-Identifier: GPL-2.0+
126 static void sun8i_hdmi_phy_set_polarity(struct sun8i_hdmi_phy *phy, in sun8i_hdmi_phy_set_polarity() argument
131 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in sun8i_hdmi_phy_set_polarity()
134 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in sun8i_hdmi_phy_set_polarity()
137 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG, in sun8i_hdmi_phy_set_polarity()
141 static int sun8i_a83t_hdmi_phy_config(struct dw_hdmi *hdmi, void *data, in sun8i_a83t_hdmi_phy_config() argument
145 unsigned int clk_rate = mode->crtc_clock * 1000; in sun8i_a83t_hdmi_phy_config()
146 struct sun8i_hdmi_phy *phy = data; in sun8i_a83t_hdmi_phy_config() local
148 sun8i_hdmi_phy_set_polarity(phy, mode); in sun8i_a83t_hdmi_phy_config()
150 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, in sun8i_a83t_hdmi_phy_config()
[all …]
Dsun8i_dw_hdmi.c1 // SPDX-License-Identifier: GPL-2.0+
22 struct sun8i_dw_hdmi *hdmi = encoder_to_sun8i_dw_hdmi(encoder); in sun8i_dw_hdmi_encoder_mode_set() local
24 clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000); in sun8i_dw_hdmi_encoder_mode_set()
33 sun8i_dw_hdmi_mode_valid_a83t(struct dw_hdmi *hdmi, void *data, in sun8i_dw_hdmi_mode_valid_a83t() argument
37 if (mode->clock > 297000) in sun8i_dw_hdmi_mode_valid_a83t()
44 sun8i_dw_hdmi_mode_valid_h6(struct dw_hdmi *hdmi, void *data, in sun8i_dw_hdmi_mode_valid_h6() argument
52 if (mode->clock > 594000) in sun8i_dw_hdmi_mode_valid_h6()
70 remote = of_graph_get_remote_node(node, 0, -1); in sun8i_dw_hdmi_find_possible_crtcs()
104 struct sun8i_dw_hdmi *hdmi; in sun8i_dw_hdmi_bind() local
107 if (!pdev->dev.of_node) in sun8i_dw_hdmi_bind()
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/Linux-v6.1/Documentation/devicetree/bindings/phy/
Damlogic,meson8-hdmi-tx-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/amlogic,meson8-hdmi-tx-phy.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Amlogic Meson8, Meson8b and Meson8m2 HDMI TX PHY
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13 The HDMI TX PHY node should be the child of a syscon node with the
16 compatible = "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
23 pattern: "^hdmi-phy@[0-9a-f]+$"
27 - items:
[all …]
Dqcom,hdmi-phy-other.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-other.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm Adreno/Snapdragon HDMI phy
11 - Rob Clark <robdclark@gmail.com>
16 - qcom,hdmi-phy-8660
17 - qcom,hdmi-phy-8960
18 - qcom,hdmi-phy-8974
19 - qcom,hdmi-phy-8084
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Dphy-rockchip-inno-hdmi.txt1 ROCKCHIP HDMI PHY WITH INNO IP BLOCK
4 - compatible : should be one of the listed compatibles:
5 * "rockchip,rk3228-hdmi-phy",
6 * "rockchip,rk3328-hdmi-phy";
7 - reg : Address and length of the hdmi phy control register set
8 - clocks : phandle + clock specifier for the phy clocks
9 - clock-names : string, clock name, must contain "sysclk" for system
10 control and register configuration, "refoclk" for crystal-
11 oscillator reference PLL clock input and "refpclk" for pclk-
13 - #clock-cells: should be 0.
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Dmediatek,hdmi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
16 The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
17 output and drives the HDMI pads.
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Dqcom,hdmi-phy-qmp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-qmp.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm Adreno/Snapdragon QMP HDMI phy
11 - Rob Clark <robdclark@gmail.com>
16 - qcom,hdmi-phy-8996
21 reg-names:
23 - const: hdmi_pll
24 - const: hdmi_tx_l0
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/Linux-v6.1/Documentation/devicetree/bindings/display/
Dallwinner,sun8i-a83t-hdmi-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-hdmi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A83t HDMI PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun8i-a83t-hdmi-phy
20 - allwinner,sun8i-h3-hdmi-phy
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Dallwinner,sun8i-a83t-dw-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A83t DWC HDMI TX Encoder
10 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller
11 IP with Allwinner\'s own PHY IP. It supports audio and video outputs
14 These DT bindings follow the Synopsys DWC HDMI TX bindings defined
15 in bridge/synopsys,dw-hdmi.yaml with the following device-specific
19 - Chen-Yu Tsai <wens@csie.org>
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Damlogic,meson-dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic specific extensions to the Synopsys Designware HDMI Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 - $ref: /schemas/sound/name-prefix.yaml#
18 - A Synopsys DesignWare HDMI Controller IP
19 - A TOP control block controlling the Clocks and PHY
20 - A custom HDMI PHY in order to convert video to TMDS signal
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/Linux-v6.1/drivers/gpu/drm/msm/hdmi/
Dhdmi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #include <linux/hdmi.h>
20 #include "hdmi.xml.h"
33 struct hdmi { struct
58 struct hdmi_phy *phy; member
67 /* the encoder we are hooked to (outside of hdmi block) */ argument
70 bool hdmi_mode; /* are we in hdmi mode? */ argument
112 struct hdmi *hdmi; member
117 void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on);
119 static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data) in hdmi_write() argument
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Dhdmi_bridge.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include "hdmi.h"
24 struct drm_device *dev = bridge->dev; in msm_hdmi_power_on()
26 struct hdmi *hdmi = hdmi_bridge->hdmi; in msm_hdmi_power_on() local
27 const struct hdmi_platform_config *config = hdmi->config; in msm_hdmi_power_on()
30 pm_runtime_get_sync(&hdmi->pdev->dev); in msm_hdmi_power_on()
32 ret = regulator_bulk_enable(config->pwr_reg_cnt, hdmi->pwr_regs); in msm_hdmi_power_on()
34 DRM_DEV_ERROR(dev->dev, "failed to enable pwr regulator: %d\n", ret); in msm_hdmi_power_on()
36 if (config->pwr_clk_cnt > 0) { in msm_hdmi_power_on()
37 DBG("pixclock: %lu", hdmi->pixclock); in msm_hdmi_power_on()
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Dhdmi_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include "hdmi.h"
10 static int msm_hdmi_phy_resource_init(struct hdmi_phy *phy) in msm_hdmi_phy_resource_init() argument
12 struct hdmi_phy_cfg *cfg = phy->cfg; in msm_hdmi_phy_resource_init()
13 struct device *dev = &phy->pdev->dev; in msm_hdmi_phy_resource_init()
16 phy->regs = devm_kcalloc(dev, cfg->num_regs, sizeof(phy->regs[0]), in msm_hdmi_phy_resource_init()
18 if (!phy->regs) in msm_hdmi_phy_resource_init()
19 return -ENOMEM; in msm_hdmi_phy_resource_init()
21 phy->clks = devm_kcalloc(dev, cfg->num_clks, sizeof(phy->clks[0]), in msm_hdmi_phy_resource_init()
23 if (!phy->clks) in msm_hdmi_phy_resource_init()
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/Linux-v6.1/Documentation/devicetree/bindings/display/samsung/
Dsamsung,exynos-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC HDMI
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,exynos4210-hdmi
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/Linux-v6.1/drivers/phy/mediatek/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the phy drivers.
6 obj-$(CONFIG_PHY_MTK_DP) += phy-mtk-dp.o
7 obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
8 obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
9 obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
10 obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
12 phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
13 phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
14 phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt8173.o
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Dphy-mtk-hdmi.c1 // SPDX-License-Identifier: GPL-2.0
7 #include "phy-mtk-hdmi.h"
9 static int mtk_hdmi_phy_power_on(struct phy *phy);
10 static int mtk_hdmi_phy_power_off(struct phy *phy);
23 static int mtk_hdmi_phy_power_on(struct phy *phy) in mtk_hdmi_phy_power_on() argument
25 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy); in mtk_hdmi_phy_power_on()
28 ret = clk_prepare_enable(hdmi_phy->pll); in mtk_hdmi_phy_power_on()
32 hdmi_phy->conf->hdmi_phy_enable_tmds(hdmi_phy); in mtk_hdmi_phy_power_on()
36 static int mtk_hdmi_phy_power_off(struct phy *phy) in mtk_hdmi_phy_power_off() argument
38 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy); in mtk_hdmi_phy_power_off()
[all …]
/Linux-v6.1/drivers/gpu/drm/bridge/synopsys/
Ddw-hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
12 #include <linux/hdmi.h>
20 #include <linux/dma-mapping.h>
23 #include <media/cec-notifier.h>
25 #include <uapi/linux/media-bus-format.h>
38 #include "dw-hdmi-audio.h"
39 #include "dw-hdmi-cec.h"
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/Linux-v6.1/drivers/gpu/drm/sti/
Dsti_hdmi_tx3g4c28phy.c1 // SPDX-License-Identifier: GPL-2.0
70 * sti_hdmi_tx3g4c28phy_start - Start hdmi phy macro cell tx3g4c28
72 * @hdmi: pointer on the hdmi internal structure
76 static bool sti_hdmi_tx3g4c28phy_start(struct sti_hdmi *hdmi) in sti_hdmi_tx3g4c28phy_start() argument
78 u32 ckpxpll = hdmi->mode.clock * 1000; in sti_hdmi_tx3g4c28phy_start()
114 * Configure and power up the PHY PLL in sti_hdmi_tx3g4c28phy_start()
116 hdmi->event_received = false; in sti_hdmi_tx3g4c28phy_start()
118 hdmi_write(hdmi, (pllctrl | PLL_CFG_EN), HDMI_SRZ_PLL_CFG); in sti_hdmi_tx3g4c28phy_start()
121 wait_event_interruptible_timeout(hdmi->wait_event, in sti_hdmi_tx3g4c28phy_start()
122 hdmi->event_received == true, in sti_hdmi_tx3g4c28phy_start()
[all …]
Dsti_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/hdmi.h>
13 #include <media/cec-notifier.h>
25 bool (*start)(struct sti_hdmi *hdmi);
26 void (*stop)(struct sti_hdmi *hdmi);
39 * STI hdmi structure
44 * @regs: hdmi register
46 * @clk_pix: hdmi pixel clock
47 * @clk_tmds: hdmi tmds clock
48 * @clk_phy: hdmi phy clock
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/Linux-v6.1/drivers/gpu/drm/msm/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 ccflags-y := -I $(srctree)/$(src)
3 ccflags-y += -I $(srctree)/$(src)/disp/dpu1
4 ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(srctree)/$(src)/dsi
5 ccflags-$(CONFIG_DRM_MSM_DP) += -I $(srctree)/$(src)/dp
7 msm-y := \
20 msm-$(CONFIG_DRM_MSM_HDMI) += \
21 hdmi/hdmi.o \
22 hdmi/hdmi_audio.o \
23 hdmi/hdmi_bridge.o \
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
107 bool "Enable DSI 28nm PHY driver in MSM DRM"
111 Choose this option if the 28nm DSI PHY is used on the platform.
114 bool "Enable DSI 20nm PHY driver in MSM DRM"
118 Choose this option if the 20nm DSI PHY is used on the platform.
121 bool "Enable DSI 28nm 8960 PHY driver in MSM DRM"
125 Choose this option if the 28nm DSI PHY 8960 variant is used on the
129 bool "Enable DSI 14nm PHY driver in MSM DRM (used by MSM8996/APQ8096)"
133 Choose this option if DSI PHY on 8996 is used on the platform.
136 bool "Enable DSI 10nm PHY driver in MSM DRM (used by SDM845)"
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/display/rockchip/
Drockchip,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip DWC HDMI TX Encoder
10 - Mark Yao <markyao0591@gmail.com>
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
14 with a companion PHY IP.
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
22 - rockchip,rk3228-dw-hdmi
[all …]
/Linux-v6.1/drivers/gpu/drm/omapdrm/dss/
Dhdmi5.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * HDMI driver for OMAP5
5 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
14 #define DSS_SUBSYS_NAME "HDMI"
31 #include <sound/omap-hdmi-audio.h>
41 static int hdmi_runtime_get(struct omap_hdmi *hdmi) in hdmi_runtime_get() argument
47 r = pm_runtime_get_sync(&hdmi->pdev->dev); in hdmi_runtime_get()
49 pm_runtime_put_noidle(&hdmi->pdev->dev); in hdmi_runtime_get()
55 static void hdmi_runtime_put(struct omap_hdmi *hdmi) in hdmi_runtime_put() argument
61 r = pm_runtime_put_sync(&hdmi->pdev->dev); in hdmi_runtime_put()
[all …]
/Linux-v6.1/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi5.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * HDMI driver for OMAP5
14 #define DSS_SUBSYS_NAME "HDMI"
31 #include <sound/omap-hdmi-audio.h>
37 static struct omap_hdmi hdmi; variable
45 r = pm_runtime_resume_and_get(&hdmi.pdev->dev); in hdmi_runtime_get()
58 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
59 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
75 * time, turn off the PHY, clear interrupts, and restart, which in hdmi_irq_handler()
84 * setting the PHY to LDOON. To ignore those, we force the RXDET in hdmi_irq_handler()
[all …]
/Linux-v6.1/drivers/gpu/drm/rockchip/
Ddw_hdmi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/phy/phy.h>
39 /* need to be unset if hdmi or i2c should control voltage */
61 * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
63 * @lcdsel_big: reg value of selecting vop big for HDMI
64 * @lcdsel_lit: reg value of selecting vop little for HDMI
79 struct dw_hdmi *hdmi; member
82 struct phy *phy; member
201 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) in rockchip_hdmi_parse_dt() argument
203 struct device_node *np = hdmi->dev->of_node; in rockchip_hdmi_parse_dt()
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