Lines Matching +full:hdmi +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/phy/phy.h>
39 /* need to be unset if hdmi or i2c should control voltage */
61 * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
63 * @lcdsel_big: reg value of selecting vop big for HDMI
64 * @lcdsel_lit: reg value of selecting vop little for HDMI
79 struct dw_hdmi *hdmi; member
82 struct phy *phy; member
201 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) in rockchip_hdmi_parse_dt() argument
203 struct device_node *np = hdmi->dev->of_node; in rockchip_hdmi_parse_dt()
205 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in rockchip_hdmi_parse_dt()
206 if (IS_ERR(hdmi->regmap)) { in rockchip_hdmi_parse_dt()
207 DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,grf\n"); in rockchip_hdmi_parse_dt()
208 return PTR_ERR(hdmi->regmap); in rockchip_hdmi_parse_dt()
211 hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "ref"); in rockchip_hdmi_parse_dt()
212 if (!hdmi->ref_clk) in rockchip_hdmi_parse_dt()
213 hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "vpll"); in rockchip_hdmi_parse_dt()
215 if (PTR_ERR(hdmi->ref_clk) == -EPROBE_DEFER) { in rockchip_hdmi_parse_dt()
216 return -EPROBE_DEFER; in rockchip_hdmi_parse_dt()
217 } else if (IS_ERR(hdmi->ref_clk)) { in rockchip_hdmi_parse_dt()
218 DRM_DEV_ERROR(hdmi->dev, "failed to get reference clock\n"); in rockchip_hdmi_parse_dt()
219 return PTR_ERR(hdmi->ref_clk); in rockchip_hdmi_parse_dt()
222 hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf"); in rockchip_hdmi_parse_dt()
223 if (PTR_ERR(hdmi->grf_clk) == -ENOENT) { in rockchip_hdmi_parse_dt()
224 hdmi->grf_clk = NULL; in rockchip_hdmi_parse_dt()
225 } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) { in rockchip_hdmi_parse_dt()
226 return -EPROBE_DEFER; in rockchip_hdmi_parse_dt()
227 } else if (IS_ERR(hdmi->grf_clk)) { in rockchip_hdmi_parse_dt()
228 DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n"); in rockchip_hdmi_parse_dt()
229 return PTR_ERR(hdmi->grf_clk); in rockchip_hdmi_parse_dt()
232 hdmi->avdd_0v9 = devm_regulator_get(hdmi->dev, "avdd-0v9"); in rockchip_hdmi_parse_dt()
233 if (IS_ERR(hdmi->avdd_0v9)) in rockchip_hdmi_parse_dt()
234 return PTR_ERR(hdmi->avdd_0v9); in rockchip_hdmi_parse_dt()
236 hdmi->avdd_1v8 = devm_regulator_get(hdmi->dev, "avdd-1v8"); in rockchip_hdmi_parse_dt()
237 if (IS_ERR(hdmi->avdd_1v8)) in rockchip_hdmi_parse_dt()
238 return PTR_ERR(hdmi->avdd_1v8); in rockchip_hdmi_parse_dt()
244 dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, in dw_hdmi_rockchip_mode_valid() argument
249 int pclk = mode->clock * 1000; in dw_hdmi_rockchip_mode_valid()
279 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); in dw_hdmi_rockchip_encoder_mode_set() local
281 clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000); in dw_hdmi_rockchip_encoder_mode_set()
286 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); in dw_hdmi_rockchip_encoder_enable() local
290 if (hdmi->chip_data->lcdsel_grf_reg < 0) in dw_hdmi_rockchip_encoder_enable()
293 ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); in dw_hdmi_rockchip_encoder_enable()
295 val = hdmi->chip_data->lcdsel_lit; in dw_hdmi_rockchip_encoder_enable()
297 val = hdmi->chip_data->lcdsel_big; in dw_hdmi_rockchip_encoder_enable()
299 ret = clk_prepare_enable(hdmi->grf_clk); in dw_hdmi_rockchip_encoder_enable()
301 DRM_DEV_ERROR(hdmi->dev, "failed to enable grfclk %d\n", ret); in dw_hdmi_rockchip_encoder_enable()
305 ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val); in dw_hdmi_rockchip_encoder_enable()
307 DRM_DEV_ERROR(hdmi->dev, "Could not write to GRF: %d\n", ret); in dw_hdmi_rockchip_encoder_enable()
309 clk_disable_unprepare(hdmi->grf_clk); in dw_hdmi_rockchip_encoder_enable()
310 DRM_DEV_DEBUG(hdmi->dev, "vop %s output to hdmi\n", in dw_hdmi_rockchip_encoder_enable()
321 s->output_mode = ROCKCHIP_OUT_MODE_AAAA; in dw_hdmi_rockchip_encoder_atomic_check()
322 s->output_type = DRM_MODE_CONNECTOR_HDMIA; in dw_hdmi_rockchip_encoder_atomic_check()
339 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_genphy_init() local
341 return phy_power_on(hdmi->phy); in dw_hdmi_rockchip_genphy_init()
346 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_genphy_disable() local
348 phy_power_off(hdmi->phy); in dw_hdmi_rockchip_genphy_disable()
353 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rk3228_setup_hpd() local
357 regmap_write(hdmi->regmap, in dw_hdmi_rk3228_setup_hpd()
364 regmap_write(hdmi->regmap, in dw_hdmi_rk3228_setup_hpd()
373 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rk3328_read_hpd() local
379 regmap_write(hdmi->regmap, in dw_hdmi_rk3328_read_hpd()
384 regmap_write(hdmi->regmap, in dw_hdmi_rk3328_read_hpd()
393 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rk3328_setup_hpd() local
397 /* Enable and map pins to 3V grf-controlled io-voltage */ in dw_hdmi_rk3328_setup_hpd()
398 regmap_write(hdmi->regmap, in dw_hdmi_rk3328_setup_hpd()
403 regmap_write(hdmi->regmap, in dw_hdmi_rk3328_setup_hpd()
408 regmap_write(hdmi->regmap, in dw_hdmi_rk3328_setup_hpd()
424 .lcdsel_grf_reg = -1,
461 .lcdsel_grf_reg = -1,
492 .lcdsel_grf_reg = -1,
505 { .compatible = "rockchip,rk3228-dw-hdmi",
508 { .compatible = "rockchip,rk3288-dw-hdmi",
511 { .compatible = "rockchip,rk3328-dw-hdmi",
514 { .compatible = "rockchip,rk3399-dw-hdmi",
517 { .compatible = "rockchip,rk3568-dw-hdmi",
532 struct rockchip_hdmi *hdmi; in dw_hdmi_rockchip_bind() local
535 if (!pdev->dev.of_node) in dw_hdmi_rockchip_bind()
536 return -ENODEV; in dw_hdmi_rockchip_bind()
538 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); in dw_hdmi_rockchip_bind()
539 if (!hdmi) in dw_hdmi_rockchip_bind()
540 return -ENOMEM; in dw_hdmi_rockchip_bind()
542 match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node); in dw_hdmi_rockchip_bind()
543 plat_data = devm_kmemdup(&pdev->dev, match->data, in dw_hdmi_rockchip_bind()
546 return -ENOMEM; in dw_hdmi_rockchip_bind()
548 hdmi->dev = &pdev->dev; in dw_hdmi_rockchip_bind()
549 hdmi->chip_data = plat_data->phy_data; in dw_hdmi_rockchip_bind()
550 plat_data->phy_data = hdmi; in dw_hdmi_rockchip_bind()
551 encoder = &hdmi->encoder.encoder; in dw_hdmi_rockchip_bind()
553 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); in dw_hdmi_rockchip_bind()
554 rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder, in dw_hdmi_rockchip_bind()
555 dev->of_node, 0, 0); in dw_hdmi_rockchip_bind()
563 if (encoder->possible_crtcs == 0) in dw_hdmi_rockchip_bind()
564 return -EPROBE_DEFER; in dw_hdmi_rockchip_bind()
566 ret = rockchip_hdmi_parse_dt(hdmi); in dw_hdmi_rockchip_bind()
568 if (ret != -EPROBE_DEFER) in dw_hdmi_rockchip_bind()
569 DRM_DEV_ERROR(hdmi->dev, "Unable to parse OF data\n"); in dw_hdmi_rockchip_bind()
573 hdmi->phy = devm_phy_optional_get(dev, "hdmi"); in dw_hdmi_rockchip_bind()
574 if (IS_ERR(hdmi->phy)) { in dw_hdmi_rockchip_bind()
575 ret = PTR_ERR(hdmi->phy); in dw_hdmi_rockchip_bind()
576 if (ret != -EPROBE_DEFER) in dw_hdmi_rockchip_bind()
577 DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n"); in dw_hdmi_rockchip_bind()
581 ret = regulator_enable(hdmi->avdd_0v9); in dw_hdmi_rockchip_bind()
583 DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret); in dw_hdmi_rockchip_bind()
587 ret = regulator_enable(hdmi->avdd_1v8); in dw_hdmi_rockchip_bind()
589 DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret); in dw_hdmi_rockchip_bind()
593 ret = clk_prepare_enable(hdmi->ref_clk); in dw_hdmi_rockchip_bind()
595 DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n", in dw_hdmi_rockchip_bind()
600 if (hdmi->chip_data == &rk3568_chip_data) { in dw_hdmi_rockchip_bind()
601 regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1, in dw_hdmi_rockchip_bind()
611 platform_set_drvdata(pdev, hdmi); in dw_hdmi_rockchip_bind()
613 hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data); in dw_hdmi_rockchip_bind()
619 if (IS_ERR(hdmi->hdmi)) { in dw_hdmi_rockchip_bind()
620 ret = PTR_ERR(hdmi->hdmi); in dw_hdmi_rockchip_bind()
628 clk_disable_unprepare(hdmi->ref_clk); in dw_hdmi_rockchip_bind()
630 regulator_disable(hdmi->avdd_1v8); in dw_hdmi_rockchip_bind()
632 regulator_disable(hdmi->avdd_0v9); in dw_hdmi_rockchip_bind()
640 struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); in dw_hdmi_rockchip_unbind() local
642 dw_hdmi_unbind(hdmi->hdmi); in dw_hdmi_rockchip_unbind()
643 clk_disable_unprepare(hdmi->ref_clk); in dw_hdmi_rockchip_unbind()
645 regulator_disable(hdmi->avdd_1v8); in dw_hdmi_rockchip_unbind()
646 regulator_disable(hdmi->avdd_0v9); in dw_hdmi_rockchip_unbind()
656 return component_add(&pdev->dev, &dw_hdmi_rockchip_ops); in dw_hdmi_rockchip_probe()
661 component_del(&pdev->dev, &dw_hdmi_rockchip_ops); in dw_hdmi_rockchip_remove()
668 struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); in dw_hdmi_rockchip_resume() local
670 dw_hdmi_resume(hdmi->hdmi); in dw_hdmi_rockchip_resume()
683 .name = "dwhdmi-rockchip",