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/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/
Dqcom,pmic-mpp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,pmic-mpp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PMIC Multi-Purpose Pin (MPP) block
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 This binding describes the MPP block(s) found in the 8xxx series of
19 - enum:
20 - qcom,pm8018-mpp
21 - qcom,pm8019-mpp
[all …]
Dmarvell,orion-pinctrl.txt1 * Marvell Orion SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f5181-pinctrl",
8 "marvell,88f5181l-pinctrl",
9 "marvell,88f5182-pinctrl",
10 "marvell,88f5281-pinctrl"
12 - reg: two register areas, the first one describing the first two
13 contiguous MPP registers, and the second one describing the single
14 final MPP register, separated from the previous one.
16 Available mpp pins/groups and functions:
[all …]
Dmarvell,dove-pinctrl.txt1 * Marvell Dove SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
11 Available mpp pins/groups and functions:
12 Note: brackets (x) are not part of the mpp name for marvell,function and given
18 mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
20 mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
[all …]
Dmarvell,armada-375-pinctrl.txt1 * Marvell Armada 375 SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6720-pinctrl"
8 - reg: register specifier of MPP registers
10 Available mpp pins/groups and functions:
11 Note: brackets (x) are not part of the mpp name for marvell,function and given
16 mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1)
17 mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi)
18 mpp2 2 gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi)
19 mpp3 3 gpio, dev(ad5), ptp(trig), led(p3), audio(mclk)
[all …]
Dmarvell,armada-xp-pinctrl.txt1 * Marvell Armada XP SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
8 "marvell,mv78460-pinctrl"
9 - reg: register specifier of MPP registers
13 Available mpp pins/groups and functions:
14 Note: brackets (x) are not part of the mpp name for marvell,function and given
21 mpp0 0 gpio, ge0(txclkout), lcd(d0)
22 mpp1 1 gpio, ge0(txd0), lcd(d1)
23 mpp2 2 gpio, ge0(txd1), lcd(d2)
[all …]
Dmarvell,armada-370-pinctrl.txt1 * Marvell Armada 370 SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6710-pinctrl"
8 - reg: register specifier of MPP registers
10 Available mpp pins/groups and functions:
11 Note: brackets (x) are not part of the mpp name for marvell,function and given
16 mpp0 0 gpio, uart0(rxd)
18 mpp2 2 gpio, i2c0(sck), uart0(txd)
19 mpp3 3 gpio, i2c0(sda), uart0(rxd)
20 mpp4 4 gpio, vdd(cpu-pd)
[all …]
Dmarvell,armada-38x-pinctrl.txt1 * Marvell Armada 380/385 SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or
8 "marvell,88f6828-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
12 Available mpp pins/groups and functions:
13 Note: brackets (x) are not part of the mpp name for marvell,function and given
18 mpp0 0 gpio, ua0(rxd)
19 mpp1 1 gpio, ua0(txd)
20 mpp2 2 gpio, i2c0(sck)
[all …]
Dmarvell,armada-39x-pinctrl.txt1 * Marvell Armada 39x SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or
8 "marvell,88f6928-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
12 Available mpp pins/groups and functions:
13 Note: brackets (x) are not part of the mpp name for marvell,function and given
18 mpp0 0 gpio, ua0(rxd)
19 mpp1 1 gpio, ua0(txd)
20 mpp2 2 gpio, i2c0(sck)
[all …]
Dmarvell,armada-98dx3236-pinctrl.txt1 * Marvell 98dx3236 pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"
8 - reg: register specifier of MPP registers
15 mpp1 1 gpio, spi0(miso), dev(ad9)
17 mpp3 3 gpio, spi0(cs0), dev(ad11)
18 mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
19 mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs)
21 mpp7 7 gpio, sd0(d0), dev(ale0)
22 mpp8 8 gpio, sd0(d1), dev(ale1)
[all …]
/Linux-v6.1/arch/arm/mach-dove/
Dmpp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-dove/mpp.c
5 * MPP functions for Marvell Dove SoCs
9 #include <linux/gpio.h>
11 #include <plat/mpp.h>
12 #include <plat/orion-gpio.h>
14 #include "mpp.h"
21 /* Map a group to a range of GPIO pins in that group */
45 /* Enable gpio for a range of pins. mode should be a combination of
55 /* Dump all the extra MPP registers. The platform code will dump the
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dorion5x-rd88f5182-nas.dts1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include "orion5x-mv88f5182.dtsi"
11 compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x";
20 stdout-path = &uart0;
30 gpio-leds {
31 compatible = "gpio-leds";
32 pinctrl-0 = <&pmx_debug_led>;
[all …]
Dqcom-pm8841.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/irq.h>
3 #include <dt-bindings/spmi/spmi.h>
8 compatible = "qcom,pm8841", "qcom,spmi-pmic";
10 #address-cells = <1>;
11 #size-cells = <0>;
14 compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp";
16 gpio-controller;
17 #gpio-cells = <2>;
18 gpio-ranges = <&pm8841_mpps 0 0 4>;
[all …]
Dqcom-pma8084.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/iio/qcom,spmi-vadc.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/spmi/spmi.h>
9 compatible = "qcom,pma8084", "qcom,spmi-pmic";
11 #address-cells = <1>;
12 #size-cells = <0>;
15 compatible = "qcom,pm8941-rtc";
18 reg-names = "rtc", "alarm";
23 compatible = "qcom,pm8941-pwrkey";
[all …]
Dqcom-pm8226.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
2 #include <dt-bindings/interrupt-controller/irq.h>
3 #include <dt-bindings/spmi/spmi.h>
4 #include <dt-bindings/iio/qcom,spmi-vadc.h>
8 compatible = "qcom,pm8226", "qcom,spmi-pmic";
10 #address-cells = <1>;
11 #size-cells = <0>;
14 compatible = "qcom,pm8941-pwrkey";
18 bias-pull-up;
22 compatible = "qcom,pm8226-charger";
[all …]
/Linux-v6.1/drivers/pinctrl/mvebu/
Dpinctrl-mvebu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * struct mvebu_mpp_ctrl_data - private data for the mpp ctrl operations
29 * struct mvebu_mpp_ctrl - describe a mpp control
33 * @mpp_get: (optional) special function to get mpp setting
34 * @mpp_set: (optional) special function to set mpp setting
35 * @mpp_gpio_req: (optional) special function to request gpio
36 * @mpp_gpio_dir: (optional) special function to set gpio direction
40 * between two or more different settings, e.g. assign mpp pin 13 to
45 * to allow pin settings with varying gpio pins.
[all …]
Dpinctrl-orion.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * The first 16 MPP pins on Orion are easy to handle: they are
9 * address of the MPP device.
11 * However the last 4 MPP pins are handled by a register at offset
25 #include "pinctrl-mvebu.h"
78 MPP_VAR_FUNCTION(0x3, "gpio", NULL, V_ALL)),
80 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
83 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
85 MPP_VAR_FUNCTION(0x3, "pci-1", "pme", V_ALL)),
[all …]
/Linux-v6.1/arch/arm/plat-orion/
Dmpp.c2 * arch/arm/plat-orion/mpp.c
4 * MPP functions for Marvell orion SoCs
15 #include <linux/gpio.h>
16 #include <plat/orion-gpio.h>
17 #include <plat/mpp.h>
19 /* Address of the ith MPP control register */
34 printk(KERN_DEBUG "initial MPP regs:"); in orion_mpp_conf()
52 printk(KERN_ERR "orion_mpp_conf: invalid MPP " in orion_mpp_conf()
58 "orion_mpp_conf: requested MPP%u config " in orion_mpp_conf()
76 printk(KERN_DEBUG " final MPP regs:"); in orion_mpp_conf()
/Linux-v6.1/arch/arm/mach-mv78xx0/
Dmpp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-mv78x00/mpp.c
5 * MPP functions for Marvell MV78x00 SoCs
7 #include <linux/gpio.h>
11 #include <plat/mpp.h>
14 #include "mpp.h"
25 printk(KERN_ERR "MPP setup: unknown mv78x00 variant " in mv78xx0_variant()
/Linux-v6.1/drivers/pinctrl/qcom/
Dpinctrl-ssbi-mpp.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/pinctrl/pinconf-generic.h>
15 #include <linux/gpio/driver.h>
20 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
23 #include "../pinctrl-utils.h"
25 /* MPP registers */
29 /* MPP Type: type */
88 * struct pm8xxx_pin_data - dynamic configuration for a pin
94 * @paired: mpp operates in paired mode
95 * @output_value: logical output value of the mpp
[all …]
Dpinctrl-spmi-mpp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
6 #include <linux/gpio/driver.h>
10 #include <linux/pinctrl/pinconf-generic.h>
18 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
21 #include "../pinctrl-utils.h"
26 * Pull Up Values - it indicates whether a pull-up should be
39 /* mpp peripheral type and subtype values */
104 * struct pmic_mpp_pad - keep current MPP settings
106 * @is_enabled: Set to false when MPP should be put in high Z state.
[all …]
/Linux-v6.1/arch/arm/mach-orion5x/
Drd88f5182-setup.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-orion5x/rd88f5182-setup.c
5 * Marvell Orion-NAS Reference Design Setup
9 #include <linux/gpio.h>
20 #include <asm/mach-types.h>
24 #include "mpp.h"
28 * RD-88F5182 Info
64 .end = RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1,
68 .name = "physmap-flash",
78 * Use GPIO LED as CPU active indication
[all …]
Dts209-setup.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * QNAP TS-109/TS-209 Board Setup
7 #include <linux/gpio.h>
21 #include <asm/mach-types.h>
25 #include "mpp.h"
27 #include "tsx09-common.h"
38 * [2] 0x00000000-0x00200000 : "Kernel"
39 * [3] 0x00200000-0x00600000 : "RootFS1"
40 * [4] 0x00600000-0x00700000 : "RootFS2"
41 * [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
[all …]
/Linux-v6.1/arch/arm64/boot/dts/qcom/
Dpmi8994.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/irq.h>
3 #include <dt-bindings/spmi/spmi.h>
8 compatible = "qcom,pmi8994", "qcom,spmi-pmic";
10 #address-cells = <1>;
11 #size-cells = <0>;
14 compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio";
16 gpio-controller;
17 gpio-ranges = <&pmi8994_gpios 0 0 10>;
18 #gpio-cells = <2>;
[all …]
Dpm8994.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/iio/qcom,spmi-vadc.h>
3 #include <dt-bindings/input/linux-event-codes.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/spmi/spmi.h>
8 thermal-zones {
9 pm8994-thermal {
10 polling-delay-passive = <250>;
11 polling-delay = <1000>;
13 thermal-sensors = <&pm8994_temp>;
[all …]
Dpm8916.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/iio/qcom,spmi-vadc.h>
3 #include <dt-bindings/input/linux-event-codes.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/spmi/spmi.h>
10 compatible = "qcom,pm8916", "qcom,spmi-pmic";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "qcom,pm8916-pon";
18 mode-bootloader = <0x2>;
[all …]

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