| /Linux-v6.1/drivers/clocksource/ |
| D | timer-microchip-pit64b.c | 53 * @gclk: PIT64B's generic clock
59 struct clk *gclk; member
136 clk_disable_unprepare(timer->gclk); in mchp_pit64b_suspend()
144 clk_prepare_enable(timer->gclk); in mchp_pit64b_resume()
253 * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to
254 * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate
255 * could be changed via clock APIs. The chosen clock (pclk or gclk) could be
258 * This function, first tries to use GCLK by requesting the desired rate from
260 * requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware)
270 * | |-->gclk -->|-->| | +---------+ +-----+ |
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| /Linux-v6.1/sound/soc/atmel/ |
| D | mchp-i2s-mcc.c | 242 struct clk *gclk; member
447 ret = mchp_i2s_mcc_clk_get_rate_diff(dev->gclk, clk_rate, in mchp_i2s_mcc_config_divs()
451 dev_err(dev->dev, "gclk error for rate %lu: %d", in mchp_i2s_mcc_config_divs()
455 dev_dbg(dev->dev, "found perfect rate on gclk: %lu\n", in mchp_i2s_mcc_config_divs()
483 best_clk == dev->pclk ? "pclk" : "gclk", in mchp_i2s_mcc_config_divs()
491 if (best_clk == dev->gclk) in mchp_i2s_mcc_config_divs()
702 ret = clk_set_rate(dev->gclk, rate); in mchp_i2s_mcc_hw_params()
705 "unable to set rate %lu to GCLK: %d\n", in mchp_i2s_mcc_hw_params()
710 ret = clk_prepare(dev->gclk); in mchp_i2s_mcc_hw_params()
712 dev_err(dev->dev, "unable to prepare GCLK: %d\n", ret); in mchp_i2s_mcc_hw_params()
[all …]
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| D | atmel-classd.c | 31 struct clk *gclk; member
130 err = clk_prepare_enable(dd->gclk); in atmel_classd_cpu_dai_startup()
365 clk_disable_unprepare(dd->gclk); in atmel_classd_cpu_dai_hw_params()
367 ret = clk_set_rate(dd->gclk, sample_rates[best].gclk_rate); in atmel_classd_cpu_dai_hw_params()
377 return clk_prepare_enable(dd->gclk); in atmel_classd_cpu_dai_hw_params()
387 clk_disable_unprepare(dd->gclk); in atmel_classd_cpu_dai_shutdown()
554 dd->gclk = devm_clk_get(dev, "gclk"); in atmel_classd_probe()
555 if (IS_ERR(dd->gclk)) { in atmel_classd_probe()
556 ret = PTR_ERR(dd->gclk); in atmel_classd_probe()
|
| D | atmel-i2s.c | 197 struct clk *gclk; member
295 if (!dev->gclk) { in atmel_i2s_get_gck_param()
442 clk_disable_unprepare(dev->gclk); in atmel_i2s_switch_mck_generator()
452 ret = clk_set_rate(dev->gclk, gclk_rate); in atmel_i2s_switch_mck_generator()
456 ret = clk_prepare_enable(dev->gclk); in atmel_i2s_switch_mck_generator()
577 if (!dev->gclk) in atmel_i2s_sama5d2_mck_init()
591 return clk_set_parent(muxclk, dev->gclk); in atmel_i2s_sama5d2_mck_init()
662 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); in atmel_i2s_probe()
663 if (IS_ERR(dev->gclk)) { in atmel_i2s_probe()
664 if (PTR_ERR(dev->gclk) == -EPROBE_DEFER) in atmel_i2s_probe()
[all …]
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| D | atmel-pdmic.c | 31 struct clk *gclk; member
111 ret = clk_prepare_enable(dd->gclk); in atmel_pdmic_cpu_dai_startup()
117 clk_disable_unprepare(dd->gclk); in atmel_pdmic_cpu_dai_startup()
141 clk_disable_unprepare(dd->gclk); in atmel_pdmic_cpu_dai_shutdown()
406 gclk_rate = clk_get_rate(dd->gclk); in atmel_pdmic_cpu_dai_hw_params()
532 u32 clk_min_rate = (u32)(clk_get_rate(dd->gclk) >> 8); in atmel_pdmic_get_sample_rate()
607 dd->gclk = devm_clk_get(dev, "gclk"); in atmel_pdmic_probe()
608 if (IS_ERR(dd->gclk)) { in atmel_pdmic_probe()
609 ret = PTR_ERR(dd->gclk); in atmel_pdmic_probe()
614 /* The gclk clock frequency must always be three times in atmel_pdmic_probe()
[all …]
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| D | mchp-spdiftx.c | 197 struct clk *gclk; member
489 clk_disable_unprepare(dev->gclk); in mchp_spdiftx_hw_params()
492 ret = clk_set_rate(dev->gclk, params_rate(params) * in mchp_spdiftx_hw_params()
496 "unable to change gclk rate to: rate %u * ratio %u\n", in mchp_spdiftx_hw_params()
500 ret = clk_prepare_enable(dev->gclk); in mchp_spdiftx_hw_params()
502 dev_err(dev->dev, "unable to enable gclk: %d\n", ret); in mchp_spdiftx_hw_params()
506 dev_dbg(dev->dev, "%s(): GCLK set to %d\n", __func__, in mchp_spdiftx_hw_params()
526 clk_disable_unprepare(dev->gclk); in mchp_spdiftx_hw_free()
810 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); in mchp_spdiftx_probe()
811 if (IS_ERR(dev->gclk)) { in mchp_spdiftx_probe()
[all …]
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| D | mchp-spdifrx.c | 239 struct clk *gclk; member
449 clk_disable_unprepare(dev->gclk); in mchp_spdifrx_hw_params()
452 ret = clk_set_min_rate(dev->gclk, params_rate(params) * in mchp_spdifrx_hw_params()
456 "unable to set gclk min rate: rate %u * ratio %u + 1\n", in mchp_spdifrx_hw_params()
460 ret = clk_prepare_enable(dev->gclk); in mchp_spdifrx_hw_params()
462 dev_err(dev->dev, "unable to enable gclk: %d\n", ret); in mchp_spdifrx_hw_params()
467 dev_dbg(dev->dev, "GCLK range min set to %d\n", in mchp_spdifrx_hw_params()
479 clk_disable_unprepare(dev->gclk); in mchp_spdifrx_hw_free()
696 rate = clk_get_rate(dev->gclk); in mchp_spdifrx_rate_get()
909 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); in mchp_spdifrx_probe()
[all …]
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| D | mchp-pdmc.c | 113 struct clk *gclk; member
598 clk_disable_unprepare(dd->gclk); in mchp_pdmc_hw_params()
607 round_rate = clk_round_rate(dd->gclk, in mchp_pdmc_hw_params()
624 ret = clk_set_rate(dd->gclk, gclk_rate); in mchp_pdmc_hw_params()
626 dev_err(comp->dev, "unable to set rate %lu to GCLK: %d\n", in mchp_pdmc_hw_params()
639 clk_prepare_enable(dd->gclk); in mchp_pdmc_hw_params()
659 clk_disable_unprepare(dd->gclk); in mchp_pdmc_hw_free()
1003 dd->gclk = devm_clk_get(dev, "gclk"); in mchp_pdmc_probe()
1004 if (IS_ERR(dd->gclk)) { in mchp_pdmc_probe()
1005 ret = PTR_ERR(dd->gclk); in mchp_pdmc_probe()
|
| /Linux-v6.1/drivers/pwm/ |
| D | pwm-atmel-tcb.c | 58 struct clk *gclk; member
307 * If there is a gclk, the first divisor is actually the gclk selector in atmel_tcb_pwm_config()
309 if (tcbpwmc->gclk) in atmel_tcb_pwm_config()
426 struct clk *clk, *gclk = NULL; in atmel_tcb_pwm_probe() local
459 gclk = of_clk_get_by_name(np->parent, "gclk"); in atmel_tcb_pwm_probe()
460 if (IS_ERR(gclk)) in atmel_tcb_pwm_probe()
461 return PTR_ERR(gclk); in atmel_tcb_pwm_probe()
476 tcbpwm->gclk = gclk; in atmel_tcb_pwm_probe()
|
| /Linux-v6.1/arch/arm/boot/dts/ |
| D | emev2.dtsi | 78 compatible = "renesas,emev2-smu-gclk";
90 compatible = "renesas,emev2-smu-gclk";
127 compatible = "renesas,emev2-smu-gclk";
133 compatible = "renesas,emev2-smu-gclk";
139 compatible = "renesas,emev2-smu-gclk";
145 compatible = "renesas,emev2-smu-gclk";
151 compatible = "renesas,emev2-smu-gclk";
|
| D | am33xx-clocks.dtsi | 351 l3_gclk: clock-l3-gclk {
360 pruss_ocp_gclk: clock-pruss-ocp-gclk@530 {
468 l4_rtc_gclk: clock-l4-rtc-gclk {
477 l4hs_gclk: clock-l4hs-gclk {
486 l3s_gclk: clock-l3s-gclk {
495 l4fw_gclk: clock-l4fw-gclk {
504 l4ls_gclk: clock-l4ls-gclk {
522 cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
547 lcd_gclk: clock-lcd-gclk@534 {
|
| D | sama7g5.dtsi | 293 clock-names = "pclk", "gclk";
308 clock-names = "pclk", "gclk";
482 clock-names = "pclk", "gclk";
494 clock-names = "pclk", "gclk";
506 clock-names = "pclk", "gclk";
518 clock-names = "pclk", "gclk";
529 clock-names = "pclk", "gclk";
541 clock-names = "pclk", "gclk";
563 clock-names = "pclk", "gclk";
571 clock-names = "pclk", "gclk";
|
| D | am43xx-clocks.dtsi | 424 pruss_ocp_gclk: clock-pruss-ocp-gclk@4248 {
510 l3_gclk: clock-l3-gclk {
528 l4hs_gclk: clock-l4hs-gclk {
537 l3s_gclk: clock-l3s-gclk {
546 l4ls_gclk: clock-l4ls-gclk {
555 cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
|
| D | sama5d2.dtsi | 400 clock-names = "t0_clk", "gclk", "slow_clk";
410 clock-names = "t0_clk", "gclk", "slow_clk";
438 clock-names = "pclk", "gclk";
734 clock-names = "pclk", "gclk";
1118 clock-names = "pclk", "gclk";
1134 clock-names = "pclk", "gclk";
|
| /Linux-v6.1/Documentation/devicetree/bindings/sound/ |
| D | atmel,sama5d2-i2s.yaml | 34 with gclk when Master Mode is required.
40 - const: gclk
82 clock-names = "pclk", "gclk", "muxclk";
|
| D | mchp,spdifrx.yaml | 37 - const: gclk
72 clock-names = "pclk", "gclk";
|
| D | mchp,spdiftx.yaml | 37 - const: gclk
72 clock-names = "pclk", "gclk";
|
| D | atmel,sama5d2-classd.yaml | 41 - const: gclk
93 clock-names = "pclk", "gclk";
|
| D | atmel,sama5d2-pdmic.yaml | 36 - const: gclk
91 clock-names = "pclk", "gclk";
|
| D | microchip,pdmc.yaml | 37 - const: gclk
95 clock-names = "pclk", "gclk";
|
| D | mchp,i2s-mcc.yaml | 47 - const: gclk
105 clock-names = "pclk", "gclk";
|
| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | renesas,emev2-smu.yaml | 81 const: renesas,emev2-smu-gclk
135 compatible = "renesas,emev2-smu-gclk";
|
| /Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | nv40.c | 149 int gclk = cstate->domain[nv_clk_src_core]; in nv40_clk_calc() local
155 ret = nv40_clk_calc_pll(clk, 0x004000, gclk, in nv40_clk_calc()
169 if (sclk && sclk != gclk) { in nv40_clk_calc()
|
| /Linux-v6.1/drivers/tty/serial/ |
| D | atmel_serial.c | 114 struct clk *gclk; /* uart generic clock */ member
2127 if (__clk_is_enabled(atmel_port->gclk)) in atmel_serial_pm()
2128 clk_disable_unprepare(atmel_port->gclk); in atmel_serial_pm()
2322 * if we use the GCLK as the clock source driving the baudrate in atmel_set_termios()
2326 if (__clk_is_enabled(atmel_port->gclk)) in atmel_set_termios()
2327 clk_disable_unprepare(atmel_port->gclk); in atmel_set_termios()
2328 gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud); in atmel_set_termios()
2332 clk_set_rate(atmel_port->gclk, 16 * baud); in atmel_set_termios()
2333 ret = clk_prepare_enable(atmel_port->gclk); in atmel_set_termios()
2345 * Set the Clock Divisor for GCLK to 1. in atmel_set_termios()
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/spi/ |
| D | atmel,quadspi.yaml | 43 - enum: [ qspick, gclk ]
|
