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/Linux-v6.1/arch/arm/boot/dts/
Dintel-ixp4xx-reference-design.dtsi1 // SPDX-License-Identifier: ISC
5 * set-up for IXDP425, IXCDP1100, KIXRP435 and IXDP465.
20 stdout-path = "uart0:115200n8";
28 compatible = "i2c-gpio";
29 sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
30 scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
31 #address-cells = <1>;
32 #size-cells = <0>;
36 * Philips PCF8582C-2T/03 512byte I2C EEPROM
43 read-only;
[all …]
Darmada-388-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-88F6820)
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 /dts-v1/;
12 #include "armada-388.dtsi"
16 compatible = "marvell,a385-db", "marvell,armada388",
20 stdout-path = "serial0:115200n8";
35 internal-regs {
38 clock-frequency = <100000>;
39 audio_codec: audio-codec@4a {
[all …]
Darmada-370-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-88F6710-BP-DDR3)
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
22 /dts-v1/;
23 #include "armada-370.dtsi"
27 compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
30 stdout-path = "serial0:115200n8";
43 internal-regs {
[all …]
Darmada-370-dlink-dns327l.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for D-Link DNS-327L
12 /dts-v1/;
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include "armada-370.dtsi"
19 model = "D-Link DNS-327L";
22 "marvell,armada-370-xp";
25 stdout-path = &uart0;
38 internal-regs {
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/mtd/
Dqcom,nandc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm NAND controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - qcom,ipq806x-nand
16 - qcom,ipq4019-nand
17 - qcom,ipq6018-nand
18 - qcom,ipq8074-nand
19 - qcom,sdx55-nand
[all …]
Dfsl-upm-nand.txt1 Freescale Localbus UPM programmed to work with NAND flash
4 - compatible : "fsl,upm-nand".
5 - reg : should specify localbus chip select and size used for the chip.
6 - fsl,upm-addr-offset : UPM pattern offset for the address latch.
7 - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
10 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
12 - gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
13 (R/B#). For multi-chip devices, "n" GPIO definitions are required
17 - fsl,upm-wait-flags : add chip-dependent short delays after running the
20 - chip-delay : chip dependent delay for transferring data from array to
[all …]
/Linux-v6.1/arch/arm/mach-omap1/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
9 obj-y := io.o id.o sram-init.o sram.o time.o irq.o mux.o flash.o \
10 serial.o devices.o dma.o omap-dma.o fb.o
11 obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o timer.o
14 obj-y += mcbsp.o
17 obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o
20 obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
23 obj-$(CONFIG_PM) += pm.o sleep.o
25 i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
26 obj-y += $(i2c-omap-m) $(i2c-omap-y)
[all …]
/Linux-v6.1/arch/powerpc/boot/dts/fsl/
Dmpc8536ds.dtsi2 * MPC8536DS Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 label = "ramdisk-nor";
51 label = "diagnostic-nor";
52 read-only;
57 label = "dink-nor";
[all …]
Dp1020rdb.dtsi2 * P1020 RDB Device Tree Source stub (no addresses or top-level ranges)
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR (RO) Vitesse-7385 Firmware";
49 read-only;
56 read-only;
[all …]
Dp1020rdb-pc.dtsi2 * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
[all …]
Dp1021rdb-pc.dtsi2 * P1021 RDB Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
75 read-only;
80 /* 512KB for u-boot Bootloader Image */
[all …]
Dmpc8572ds.dtsi2 * MPC8572DS Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 label = "ramdisk-nor";
51 label = "diagnostic-nor";
52 read-only;
57 label = "dink-nor";
[all …]
Dp1025rdb.dtsi2 * P1025 RDB Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
[all …]
Dp1020rdb-pd.dts2 * P1020 RDB-PD Device Tree Source (32-bit address map)
35 /include/ "p1020si-pre.dtsi"
37 model = "fsl,P1020RDB-PD";
38 compatible = "fsl,P1020RDB-PD";
47 /* NOR, NAND flash, L2 switch and CPLD */
54 #address-cells = <1>;
55 #size-cells = <1>;
56 compatible = "cfi-flash";
58 bank-width = <2>;
59 device-width = <1>;
[all …]
Dp1021mds.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /include/ "p1021si-pre.dtsi"
25 /* NAND Flash, BCSR, PMC0/1*/
31 nand@0,0 {
32 #address-cells = <1>;
33 #size-cells = <1>;
34 compatible = "fsl,p1021-fcm-nand",
35 "fsl,elbc-fcm-nand";
40 /* 1MB for u-boot Bootloader Image */
42 label = "NAND (RO) U-Boot Image";
[all …]
Dp2041rdb.dts4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /include/ "p2041si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
61 reserved-memory {
62 #address-cells = <2>;
63 #size-cells = <2>;
66 bman_fbpr: bman-fbpr {
70 qman_fqd: qman-fqd {
[all …]
Dp3041ds.dts4 * Copyright 2010 - 2015 Freescale Semiconductor Inc.
35 /include/ "p3041si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 reserved-memory {
63 #address-cells = <2>;
64 #size-cells = <2>;
67 bman_fbpr: bman-fbpr {
71 qman_fqd: qman-fqd {
[all …]
Dp5020ds.dts4 * Copyright 2010 - 2015 Freescale Semiconductor Inc.
35 /include/ "p5020si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 reserved-memory {
63 #address-cells = <2>;
64 #size-cells = <2>;
67 bman_fbpr: bman-fbpr {
71 qman_fqd: qman-fqd {
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/
Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
24 mpp0 0 gpio, nand(io2), spi(cs)
25 mpp1 1 gpo, nand(io3), spi(mosi)
26 mpp2 2 gpo, nand(io4), spi(sck)
[all …]
/Linux-v6.1/Documentation/filesystems/
Dubifs.rst1 .. SPDX-License-Identifier: GPL-2.0
10 UBIFS file-system stands for UBI File System. UBI stands for "Unsorted
13 is completely different to any traditional file-system in Linux, like
14 Ext2, XFS, JFS, etc. UBIFS represents a separate class of file-systems
16 file-system of this class is JFFS2.
24 2 MTD devices support 3 main operations - read from some offset within an
26 eraseblock. Block devices support 2 main operations - read a whole
29 re-write its contents. Blocks may be just re-written.
30 4 Eraseblocks become worn out after some number of erase cycles -
31 typically 100K-1G for SLC NAND and NOR flashes, and 1K-10K for MLC
[all …]
/Linux-v6.1/drivers/watchdog/
Drc32434_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include <linux/errno.h> /* For the -ENODEV/... values */
22 #include <linux/fs.h> /* For file operations */
31 #include <asm/mach-rc32434/integ.h> /* For the Watchdog registers */
54 * ((2 ^ 32) - 1) / (400MHz / 2) = 21s. */
67 /* apply or and nand masks to data read from addr and write back */
68 #define SET_BITS(addr, or, nand) \ argument
69 writel((readl(&addr) | or) & ~nand, &addr)
73 int max_to = WTCOMP2SEC((u32)-1); in rc32434_wdt_set()
77 return -EINVAL; in rc32434_wdt_set()
[all …]
/Linux-v6.1/Documentation/arm/stm32/
Dstm32h750-overview.rst6 ------------
8 The STM32H750 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @480MHz
12 - 128K internal flash, 1MBytes internal RAM
13 - FMC controller to connect SDRAM, NOR and NAND memories
14 - Dual mode QSPI
15 - SD/MMC/SDIO support
16 - Ethernet controller
17 - USB OTFG FS & HS controllers
18 - I2C, SPI, CAN busses support
[all …]
Dstm32h743-overview.rst6 ------------
8 The STM32H743 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @400MHz
12 - 2MB internal flash, 1MBytes internal RAM
13 - FMC controller to connect SDRAM, NOR and NAND memories
14 - Dual mode QSPI
15 - SD/MMC/SDIO support
16 - Ethernet controller
17 - USB OTFG FS & HS controllers
18 - I2C, SPI, CAN busses support
[all …]
Dstm32f746-overview.rst6 ------------
8 The STM32F746 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @216MHz
12 - 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM)
13 - FMC controller to connect SDRAM, NOR and NAND memories
14 - Dual mode QSPI
15 - SD/MMC/SDIO support
16 - Ethernet controller
17 - USB OTFG FS & HS controllers
18 - I2C, SPI, CAN busses support
[all …]
Dstm32f769-overview.rst6 ------------
8 The STM32F769 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @216MHz
12 - 2MB internal flash, 512KBytes internal RAM (+4KB of backup SRAM)
13 - FMC controller to connect SDRAM, NOR and NAND memories
14 - Dual mode QSPI
15 - SD/MMC/SDIO support*2
16 - Ethernet controller
17 - USB OTFG FS & HS controllers
18 - I2C*4, SPI*6, CAN*3 busses support
[all …]

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