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/Linux-v5.15/Documentation/devicetree/bindings/sound/
Dsimple-card.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
14 frame-master:
15 description: Indicates dai-link frame master.
18 bitclock-master:
19 description: Indicates dai-link bit clock master
22 frame-inversion:
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Dmikroe,mikroe-proto.txt1 Mikroe-PROTO audio board
4 - compatible: "mikroe,mikroe-proto"
5 - dai-format: Must be "i2s".
6 - i2s-controller: The phandle of the I2S controller.
7 - audio-codec: The phandle of the WM8731 audio codec.
9 - model: The user-visible name of this sound complex.
10 - bitclock-master: Indicates dai-link bit clock master; for details see simple-card.txt (1).
11 - frame-master: Indicates dai-link frame master; for details see simple-card.txt (1).
13 (1) : There must be the same master for both bit and frame clocks.
17 compatible = "mikroe,mikroe-proto";
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Daudio-graph-port.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/audio-graph-port.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
15 - $ref: /schemas/graph.yaml#/$defs/port-base
21 convert-rate:
24 convert-channels:
28 "^endpoint(@[0-9a-f]+)?":
29 $ref: /schemas/graph.yaml#/$defs/endpoint-base
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Dfsl-asoc-card.txt23 "fsl,imx-audio-ac97"
25 "fsl,imx-audio-cs42888"
27 "fsl,imx-audio-cs427x"
30 "fsl,imx-audio-wm8962"
32 "fsl,imx-audio-sgtl5000"
33 (compatible with Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt)
35 "fsl,imx-audio-wm8960"
37 "fsl,imx-audio-mqs"
39 "fsl,imx-audio-wm8524"
41 "fsl,imx-audio-tlv320aic32x4"
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/Linux-v5.15/Documentation/sound/soc/
Dclocking.rst9 Master Clock
10 ------------
12 Every audio subsystem is driven by a master clock (sometimes referred to as MCLK
13 or SYSCLK). This audio master clock can be derived from a number of sources
17 Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
19 power). Other master clocks are fixed at a set frequency (i.e. crystals).
23 ----------
28 The DAI also has a frame clock to signal the start of each audio frame. This
29 clock is sometimes referred to as LRC (left right clock) or FRAME. This clock
32 Bit Clock can be generated as follows:-
[all …]
Ddai.rst16 frame (FRAME) (usually 48kHz) is always driven by the controller. Each AC97
17 frame is 21uS long and is divided into 13 time slots.
29 controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
30 usually varies depending on the sample rate and the master system clock
35 I2S has several different operating modes:-
58 Common PCM operating modes:-
61 MSB is transmitted on falling edge of first BCLK after FRAME/SYNC.
64 MSB is transmitted on rising edge of FRAME/SYNC.
/Linux-v5.15/include/linux/dma/
Dxilinx_dma.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
11 #include <linux/dma-mapping.h>
15 * struct xilinx_vdma_config - VDMA Configuration structure
16 * @frm_dly: Frame delay
17 * @gen_lock: Whether in gen-lock mode
18 * @master: Master that it syncs to
19 * @frm_cnt_en: Enable frame count enable
21 * @park_frm: Frame to park on
25 * @ext_fsync: External Frame Sync source
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/Linux-v5.15/net/hsr/
Dhsr_forward.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2011-2014 Autronica Fire and Security AS
5 * 2011-2014 Arvid Brodin, arvid.brodin@alten.se
7 * Frame router for HSR and PRP.
24 * --
25 * Or not - resetting the counter and bridging the frame would create a
29 * frame is received from a particular node, we know something is wrong.
45 if (!ether_addr_equal(eth_hdr->h_dest, in is_supervision_frame()
46 hsr->sup_multicast_addr)) in is_supervision_frame()
50 if (!(eth_hdr->h_proto == htons(ETH_P_PRP) || in is_supervision_frame()
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Dhsr_device.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2011-2014 Autronica Fire and Security AS
5 * 2011-2014 Arvid Brodin, arvid.brodin@alten.se
23 return dev && (dev->flags & IFF_UP); in is_admin_up()
34 if (dev->operstate != transition) { in __hsr_set_operstate()
35 dev->operstate = transition; in __hsr_set_operstate()
43 static void hsr_set_operstate(struct hsr_port *master, bool has_carrier) in hsr_set_operstate() argument
45 if (!is_admin_up(master->dev)) { in hsr_set_operstate()
46 __hsr_set_operstate(master->dev, IF_OPER_DOWN); in hsr_set_operstate()
51 __hsr_set_operstate(master->dev, IF_OPER_UP); in hsr_set_operstate()
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/Linux-v5.15/Documentation/networking/dsa/
Ddsa.rst22 An Ethernet switch is typically comprised of multiple front-panel ports, and one
27 gateways, or even top-of-the rack switches. This host Ethernet controller will
28 be later referred to as "master" and "cpu" in DSA terminology and code.
36 For each front-panel port, DSA will create specialized network devices which are
37 used as controlling and data-flowing endpoints for use by the Linux networking
46 - what port is this frame coming from
47 - what was the reason why this frame got forwarded
48 - how to send CPU originated traffic to specific ports
52 on Port-based VLAN IDs).
57 - the "cpu" port is the Ethernet switch facing side of the management
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/Linux-v5.15/sound/soc/ti/
Ddavinci-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * based on davinci-mcasp.c DT support
31 #include "edma-pcm.h"
32 #include "davinci-i2s.h"
34 #define DRV_NAME "davinci-i2s"
39 * - This driver supports the "Audio Serial Port" (ASP),
42 * - But it labels it a "Multi-channel Buffered Serial Port"
44 * backward-compatible, possibly explaining that confusion.
46 * - OMAP chips have a controller called McBSP, which is
49 * - Newer DaVinci chips have a controller called McASP,
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/Linux-v5.15/arch/arm/boot/dts/
Dpxa300-raumfeld-connector.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "pxa300-raumfeld-common.dtsi"
6 #include "pxa300-raumfeld-tuneable-clock.dtsi"
10 compatible = "raumfeld,raumfeld-connector-pxa303", "marvell,pxa300";
13 compatible = "simple-audio-card";
14 simple-audio-card,name = "Raumfeld Connector";
15 #address-cells = <1>;
16 #size-cells = <0>;
18 simple-audio-card,dai-link@0 {
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Dpxa300-raumfeld-speaker-one.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "pxa300-raumfeld-common.dtsi"
9 compatible = "raumfeld,raumfeld-speaker-one-pxa303", "marvell,pxa300";
13 #sound-dai-cells = <0>;
14 Vdd-supply = <&reg_3v3>;
15 Vdda-supply = <&reg_va_5v0>;
18 xo_11mhz: oscillator-11mhz {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
[all …]
/Linux-v5.15/drivers/net/wireless/ti/wl12xx/
Dconf.h1 /* SPDX-License-Identifier: GPL-2.0-only */
39 * in WLAN / BT master basic rate
41 * Range: 0 - 255 (ms)
50 * Range: 0 - 255 (ms)
57 * in WLAN / BT master EDR
59 * Range: 0 - 255 (ms)
68 * Range: 0 - 255 (ms)
75 * in WLAN PSM / BT master/slave BR
77 * Range: 0 - 255 (ms)
84 * in WLAN PSM / BT master/slave EDR
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/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dfsl-ls1012a-oxalis.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
11 #include "fsl-ls1012a.dtsi"
15 compatible = "ebs-systart,oxalis", "fsl,ls1012a";
17 sys_mclk: clock-mclk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <25000000>;
23 reg_1p8v: regulator-1p8v {
24 compatible = "regulator-fixed";
[all …]
Dfsl-ls1012a-frdm.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include "fsl-ls1012a.dtsi"
15 compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
17 sys_mclk: clock-mclk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <25000000>;
23 reg_1p8v: regulator-1p8v {
[all …]
Dfsl-ls1028a-kontron-sl28-var3-ads2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board on a SMARC Eval 2.0
10 /dts-v1/;
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls1028a-kontron-sl28.dts"
16 model = "Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier";
17 compatible = "kontron,sl28-var3-ads2", "kontron,sl28-var3",
20 pwm-fan {
21 compatible = "pwm-fan";
22 cooling-min-state = <0>;
[all …]
Dfsl-ls1012a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "fsl-ls1012a.dtsi"
14 compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
21 sys_mclk: clock-mclk {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <24576000>;
27 reg_3p3v: regulator-3p3v {
28 compatible = "regulator-fixed";
[all …]
/Linux-v5.15/drivers/atm/
Dsuni.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * drivers/atm/suni.h - S/UNI PHY driver
6 /* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */
17 #define SUNI_MRI 0x00 /* Master Reset and Identity / Load
19 #define SUNI_MC 0x01 /* Master Configuration */
20 #define SUNI_MIS 0x02 /* Master Interrupt Status */
22 #define SUNI_MCM 0x04 /* Master Clock Monitor */
23 #define SUNI_MCT 0x05 /* Master Control */
26 /* 0x08-0x0F reserved */
29 #define SUNI_RSOP_SBL 0x12 /* RSOP Section BIP-8 LSB */
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/Linux-v5.15/include/linux/soundwire/
Dsdw.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
25 /* SDW Master Device Number, not supported yet */
29 /* frame shape defines */
71 * enum sdw_slave_status - Slave status
89 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
90 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
100 * enum sdw_command_response - Command response as defined by SDW spec
186 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
197 * enum sdw_dpn_type - Data port types
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/Linux-v5.15/net/dsa/
Dtag_sja1105.c1 // SPDX-License-Identifier: GPL-2.0
19 /* Trap-to-host format (no trailer present) */
29 /* Meta frame format (for 2-step TX timestamps) */
62 /* Similar to is_link_local_ether_addr(hdr->h_dest) but also covers PTP */
66 u64 dmac = ether_addr_to_u64(hdr->h_dest); in sja1105_is_link_local()
68 if (ntohs(hdr->h_proto) == ETH_P_SJA1105_META) in sja1105_is_link_local()
93 * Structure of the meta-data follow-up frame. in sja1105_meta_unpack()
95 * while unpacking the meta frame. in sja1105_meta_unpack()
99 * same and the E/T puts zeroes in the high-order byte, use in sja1105_meta_unpack()
102 packing(buf, &meta->tstamp, 31, 0, 4, UNPACK, 0); in sja1105_meta_unpack()
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/Linux-v5.15/arch/alpha/kernel/
Derr_titan.c1 // SPDX-License-Identifier: GPL-2.0
58 nxs -= 4; in titan_parse_c_misc()
66 printk("%s Non-existent memory access from: %s %d\n", in titan_parse_c_misc()
119 " Source: %-6s Command: %-8s Syndrome: 0x%08x\n" in titan_parse_p_serror()
198 * master aborts as the BIOS probes the capabilities of the in titan_parse_p_perror()
200 * is a master abort (No DevSel as PCI Master) and the command in titan_parse_p_perror()
205 * dismiss master aborts to VGA frame buffer space in titan_parse_p_perror()
206 * (0xA0000 - 0xC0000) and legacy BIOS space (0xC0000 - 0x100000) in titan_parse_p_perror()
211 * can cause multiple master aborts and the error interrupt can in titan_parse_p_perror()
213 * it is possible for a second master abort to occur between the in titan_parse_p_perror()
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/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_optc.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
31 optc1->tg_regs->reg
34 optc1->base.ctx
38 optc1->tg_shift->field_name, optc1->tg_mask->field_name
42 * Enable CRTC - call ASIC Control Object to enable Timing generator.
56 OPTC_SEG0_SRC_SEL, optc->inst); in optc2_enable_crtc()
78 * Options: anytime, start of frame, dp start of frame (range timing)
102 * set one of the OTGs to be the master (OTG_GSL_MASTER_EN = 1) and the rest are slaves. in optc2_set_gsl()
105 OTG_GSL0_EN, params->gsl0_en, in optc2_set_gsl()
106 OTG_GSL1_EN, params->gsl1_en, in optc2_set_gsl()
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/Linux-v5.15/sound/soc/bcm/
Dbcm2835-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
23 * Copyright 2007-2010 Freescale Semiconductor, Inc.
108 /* Frame length register is 10 bit, maximum length 1024 */
130 unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK; in bcm2835_i2s_start_clock() local
132 if (dev->clk_prepared) in bcm2835_i2s_start_clock()
135 switch (master) { in bcm2835_i2s_start_clock()
138 clk_prepare_enable(dev->clk); in bcm2835_i2s_start_clock()
139 dev->clk_prepared = true; in bcm2835_i2s_start_clock()
148 if (dev->clk_prepared) in bcm2835_i2s_stop_clock()
149 clk_disable_unprepare(dev->clk); in bcm2835_i2s_stop_clock()
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/Linux-v5.15/drivers/spi/
Dspi-uniphier.c1 // SPDX-License-Identifier: GPL-2.0
2 // spi-uniphier.c - Socionext UniPhier SPI controller driver
4 // Copyright 2016-2018 Socionext Inc.
29 struct spi_master *master; member
113 val = readl(priv->base + SSI_IE); in uniphier_spi_irq_enable()
115 writel(val, priv->base + SSI_IE); in uniphier_spi_irq_enable()
123 val = readl(priv->base + SSI_IE); in uniphier_spi_irq_disable()
125 writel(val, priv->base + SSI_IE); in uniphier_spi_irq_disable()
130 struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master); in uniphier_spi_set_mode()
140 * frame setting in uniphier_spi_set_mode()
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