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/Linux-v6.1/Documentation/devicetree/bindings/interrupt-controller/
Dapple,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
22 - Automatic masking on event delivery (auto-ack)
23 - Software triggering (ORed with hw line)
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/Linux-v6.1/fs/fuse/
Ddev.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
37 * Lockless access is OK, because file->private data is set in fuse_get_dev()
40 return READ_ONCE(file->private_data); in fuse_get_dev()
45 INIT_LIST_HEAD(&req->list); in fuse_request_init()
46 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
47 init_waitqueue_head(&req->waitq); in fuse_request_init()
48 refcount_set(&req->count, 1); in fuse_request_init()
49 __set_bit(FR_PENDING, &req->flags); in fuse_request_init()
50 req->fm = fm; in fuse_request_init()
69 refcount_inc(&req->count); in __fuse_get_request()
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Dfuse_i.h3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
23 #include <linux/backing-dev.h>
41 /** Bias for fi->writectr, meaning new writepages must not be sent */
87 /** The sticky bit in inode->i_mode may have been removed, so
100 /* Files usable in writepage. Protected by fi->lock */
221 /** RB node to be linked on fuse_conn->polled_files */
337 * - FR_ABORTED
338 * - FR_LOCKED (may also be modified under fc->lock, tested under both)
371 /** virtio-fs's physically contiguous buffer for in and out args */
384 * Input queue signalling is device-specific. For example, the /dev/fuse file
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Dvirtio_fs.c1 // SPDX-License-Identifier: GPL-2.0
3 * virtio-fs: Virtio Filesystem
28 /* List of virtio-fs device instances and a lock for the list. Also provides
41 /* Per-virtqueue state */
44 struct virtqueue *vq; /* protected by ->lock */
56 /* A virtio-fs device instance */
114 struct fuse_fs_context *ctx = fsc->fs_private; in virtio_fs_parse_param()
123 ctx->dax_mode = FUSE_DAX_ALWAYS; in virtio_fs_parse_param()
126 ctx->dax_mode = result.uint_32; in virtio_fs_parse_param()
129 return -EINVAL; in virtio_fs_parse_param()
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/Linux-v6.1/drivers/irqchip/
Dirq-apple-aic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on irq-lpc32xx:
6 * Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com>
7 * Based on irq-bcm2836:
14 * - 896 level-triggered hardware IRQs
15 * - Single mask bit per IRQ
16 * - Per-IRQ affinity setting
17 * - Automatic masking on event delivery (auto-ack)
18 * - Software triggering (ORed with hw line)
19 * - 2 per-CPU IPIs (meant as "self" and "other", but they are
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Dirq-bcm2835.c1 // SPDX-License-Identifier: GPL-2.0+
29 * The FIQ control register:
30 * Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
31 * Bit 7: Enable FIQ generation
34 * An interrupt must be disabled before configuring it for FIQ generation
94 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]); in armctrl_mask_irq()
99 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]); in armctrl_unmask_irq()
103 .name = "ARMCTRL-level",
113 return -EINVAL; in armctrl_xlate()
116 return -EINVAL; in armctrl_xlate()
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Dirq-gic-v3.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
23 #include <linux/irqchip/arm-gic-common.h>
24 #include <linux/irqchip/arm-gic-v3.h>
25 #include <linux/irqchip/irq-partition-percpu.h>
32 #include "irq-gic-common.h"
70 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
74 * When security is enabled, non-secure priority values from the (re)distributor
78 * If SCR_EL3.FIQ == 1, the values written to/read from PMR and RPR at non-secure
80 * from the (re)distributor when security is enabled. When SCR_EL3.FIQ == 0,
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/Linux-v6.1/Documentation/devicetree/bindings/sound/
Dfsl,ssi.txt4 be programmed in AC97, I2S, left-justified, or right-justified modes.
7 - compatible: Compatible list, should contain one of the following
9 fsl,mpc8610-ssi
10 fsl,imx51-ssi
11 fsl,imx35-ssi
12 fsl,imx21-ssi
13 - cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on.
14 - reg: Offset and length of the register set for the device.
15 - interrupts: <a b> where a is the interrupt number and b is a
21 - fsl,fifo-depth: The number of elements in the transmit and receive FIFOs.
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/Linux-v6.1/arch/arm/mach-imx/
Dtzic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
20 #include "irq-common.h"
54 unsigned int index, mask, value; in tzic_set_irq_fiq() local
56 index = hwirq >> 5; in tzic_set_irq_fiq()
57 if (unlikely(index >= 4)) in tzic_set_irq_fiq()
58 return -EINVAL; in tzic_set_irq_fiq()
61 value = imx_readl(tzic_base + TZIC_INTSEC0(index)) | mask; in tzic_set_irq_fiq()
64 imx_writel(value, tzic_base + TZIC_INTSEC0(index)); in tzic_set_irq_fiq()
76 int idx = d->hwirq >> 5; in tzic_irq_suspend()
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/Linux-v6.1/sound/soc/fsl/
Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
16 // we receive in our (PCM-) data stream. The only chance we have is to
17 // manually skip this data in the FIQ handler. With sampling rates different
19 // between pcm data and GPIO status data changes. Our FIQ handler is not
43 #include <linux/dma/imx-dma.h>
53 #include "imx-pcm.h"
55 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
66 * (bit-endianness must match byte-endianness). Processors typically write
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/Linux-v6.1/arch/arm64/boot/dts/apple/
Dt8103.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 compatible = "apple,t8103", "apple,arm-platform";
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <2>;
23 #size-cells = <0>;
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/Linux-v6.1/drivers/clocksource/
Dtimer-tegra186.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019-2020 NVIDIA Corporation. All rights reserved.
64 unsigned int index; member
72 unsigned int index; member
96 writel_relaxed(value, tmr->regs + offset); in tmr_writel()
101 writel_relaxed(value, wdt->regs + offset); in wdt_writel()
106 return readl_relaxed(wdt->regs + offset); in wdt_readl()
110 unsigned int index) in tegra186_tmr_create() argument
112 unsigned int offset = 0x10000 + index * 0x10000; in tegra186_tmr_create()
115 tmr = devm_kzalloc(tegra->dev, sizeof(*tmr), GFP_KERNEL); in tegra186_tmr_create()
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/Linux-v6.1/arch/arm/probes/kprobes/
Dtest-core.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/probes/kprobes/test-core.h
41 * Store the given value into the stack buffer at [SP+index].
70 u8 index; member
107 verbose("---------------------------------------------------------\n");
134 #define TEST_ARG_MEM(index, val) \ argument
136 ".byte "#index" \n\t" \
149 ".short 50f-0f \n\t" \
150 ".short 2f-0f \n\t" \
151 ".short 99f-0f \n\t" \
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/Linux-v6.1/arch/arm64/kernel/
Dsetup.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 1995-2001 Russell King
102 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
103 * level in order to build a linear index from an
112 * Pre-scan the list of MPIDRS and filter out bits that do in smp_build_mpidr_hash()
130 fs[i] = affinity ? ffs(affinity) - 1 : 0; in smp_build_mpidr_hash()
131 bits[i] = ls - fs[i]; in smp_build_mpidr_hash()
134 * An index can be created from the MPIDR_EL1 by isolating the in smp_build_mpidr_hash()
144 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0]; in smp_build_mpidr_hash()
145 mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] - in smp_build_mpidr_hash()
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/Linux-v6.1/arch/arm64/kvm/vgic/
Dvgic-v3.c1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/irqchip/arm-gic-v3.h>
23 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; in vgic_v3_set_underflow()
25 cpuif->vgic_hcr |= ICH_HCR_UIE; in vgic_v3_set_underflow()
36 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; in vgic_v3_fold_lr_state()
37 struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3; in vgic_v3_fold_lr_state()
38 u32 model = vcpu->kvm->arch.vgic.vgic_model; in vgic_v3_fold_lr_state()
43 cpuif->vgic_hcr &= ~ICH_HCR_UIE; in vgic_v3_fold_lr_state()
45 for (lr = 0; lr < cpuif->used_lrs; lr++) { in vgic_v3_fold_lr_state()
46 u64 val = cpuif->vgic_lr[lr]; in vgic_v3_fold_lr_state()
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/Linux-v6.1/arch/arm/mach-rpc/
Decard.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 1995-2001 Russell King
11 * 08-Dec-1996 RMK Added code for the 9'th expansion card - the ether
13 * 06-May-1997 RMK Added blacklist for cards whose loader doesn't work.
14 * 12-Sep-1997 RMK Created new handling of interrupt enables/disables
15 * - cards can now register their own routine to control
17 * 29-Sep-1997 RMK Expansion card interrupt hardware not being re-enabled
20 * 15-Feb-1998 RMK Added DMA support
21 * 12-Sep-1998 RMK Added EASI support
22 * 10-Jan-1999 RMK Run loaders in a simulated RISC OS environment.
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/Linux-v6.1/arch/arm/kernel/
Dsetup.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 1995-2001 Russell King
46 #include <asm/mach-types.h>
147 u32 fiq[4]; member
307 /* I-cache aliases will be handled by D-cache aliasing code */ in cpu_has_aliasing_icache()
360 * These functions re-use the assembly code in head.S, which
520 * cpu_init - initialise one CPU.
522 * cpu_init sets up the per-CPU stacks.
545 * In Thumb-2, msr with an immediate value is not allowed. in cpu_init()
556 * setup stacks for re-entrant exception handlers in cpu_init()
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/Linux-v6.1/arch/arm/mm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
190 # ARM946E-S
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
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/Linux-v6.1/drivers/net/wireless/atmel/
Datmel.c1 /*** -*- linux-c -*- **********************************************************
5 Copyright 2000-2001 ATMEL Corporation.
6 Copyright 2003-2004 Simon Kelley.
80 over-rides any automatic selection */
100 MODULE_FIRMWARE("atmel_at76c502-wpa.bin");
102 MODULE_FIRMWARE("atmel_at76c502d-wpa.bin");
104 MODULE_FIRMWARE("atmel_at76c502e-wpa.bin");
106 MODULE_FIRMWARE("atmel_at76c502_3com-wpa.bin");
108 MODULE_FIRMWARE("atmel_at76c504-wpa.bin");
110 MODULE_FIRMWARE("atmel_at76c504_2958-wpa.bin");
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/Linux-v6.1/arch/arm/boot/compressed/
Dhead.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2002 Russell King
12 #include "efi-header.S"
20 AR_CLASS( .arch armv7-a )
21 M_CLASS( .arch armv7-m )
101 kputc #'-'
105 kputc #'-'
110 kputc #'-'
154 * in little-endian form.
234 * Booting from Angel - need to enter SVC mode and disable
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/Linux-v6.1/Documentation/virt/kvm/
Dapi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
13 - System ioctls: These query and set global attributes which affect the
17 - VM ioctls: These query and set attributes that affect an entire virtual
24 - vcpu ioctls: These query and set attributes that control the operation
32 - device ioctls: These query and set attributes that control the operation
80 facility that allows backward-compatible extensions to the API to be
104 the ioctl returns -ENOTTY.
122 -----------------------
139 -----------------
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/Linux-v6.1/
DMAINTAINERS9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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