Lines Matching +full:fiq +full:- +full:index
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019-2020 NVIDIA Corporation. All rights reserved.
64 unsigned int index; member
72 unsigned int index; member
96 writel_relaxed(value, tmr->regs + offset); in tmr_writel()
101 writel_relaxed(value, wdt->regs + offset); in wdt_writel()
106 return readl_relaxed(wdt->regs + offset); in wdt_readl()
110 unsigned int index) in tegra186_tmr_create() argument
112 unsigned int offset = 0x10000 + index * 0x10000; in tegra186_tmr_create()
115 tmr = devm_kzalloc(tegra->dev, sizeof(*tmr), GFP_KERNEL); in tegra186_tmr_create()
117 return ERR_PTR(-ENOMEM); in tegra186_tmr_create()
119 tmr->parent = tegra; in tegra186_tmr_create()
120 tmr->regs = tegra->regs + offset; in tegra186_tmr_create()
121 tmr->index = index; in tegra186_tmr_create()
122 tmr->hwirq = 0; in tegra186_tmr_create()
139 tmr_writel(wdt->tmr, 0, TMRCR); in tegra186_wdt_disable()
144 struct tegra186_timer *tegra = wdt->tmr->parent; in tegra186_wdt_enable()
148 value = TKEIE_WDT_MASK(wdt->index, 1); in tegra186_wdt_enable()
149 writel(value, tegra->regs + TKEIE(wdt->tmr->hwirq)); in tegra186_wdt_enable()
152 tmr_writel(wdt->tmr, TMRSR_INTR_CLR, TMRSR); in tegra186_wdt_enable()
155 tmr_writel(wdt->tmr, TMRCSSR_SRC_USEC, TMRCSSR); in tegra186_wdt_enable()
158 value = TMRCR_PTV(wdt->base.timeout * USEC_PER_SEC / 5) | in tegra186_wdt_enable()
160 tmr_writel(wdt->tmr, value, TMRCR); in tegra186_wdt_enable()
162 if (!wdt->locked) { in tegra186_wdt_enable()
167 value |= WDTCR_TIMER_SOURCE(wdt->tmr->index); in tegra186_wdt_enable()
176 /* enable local FIQ and remote interrupt for debug dump */ in tegra186_wdt_enable()
227 if (watchdog_active(&wdt->base)) in tegra186_wdt_set_timeout()
230 wdt->base.timeout = timeout; in tegra186_wdt_set_timeout()
232 if (watchdog_active(&wdt->base)) in tegra186_wdt_set_timeout()
247 unsigned int index) in tegra186_wdt_create() argument
254 offset += tegra->soc->num_timers * 0x10000 + index * 0x10000; in tegra186_wdt_create()
256 wdt = devm_kzalloc(tegra->dev, sizeof(*wdt), GFP_KERNEL); in tegra186_wdt_create()
258 return ERR_PTR(-ENOMEM); in tegra186_wdt_create()
260 wdt->regs = tegra->regs + offset; in tegra186_wdt_create()
261 wdt->index = index; in tegra186_wdt_create()
267 wdt->locked = true; in tegra186_wdt_create()
271 wdt->tmr = tegra186_tmr_create(tegra, source); in tegra186_wdt_create()
272 if (IS_ERR(wdt->tmr)) in tegra186_wdt_create()
273 return ERR_CAST(wdt->tmr); in tegra186_wdt_create()
275 wdt->base.info = &tegra186_wdt_info; in tegra186_wdt_create()
276 wdt->base.ops = &tegra186_wdt_ops; in tegra186_wdt_create()
277 wdt->base.min_timeout = 1; in tegra186_wdt_create()
278 wdt->base.max_timeout = 255; in tegra186_wdt_create()
279 wdt->base.parent = tegra->dev; in tegra186_wdt_create()
281 err = watchdog_init_timeout(&wdt->base, 5, tegra->dev); in tegra186_wdt_create()
283 dev_err(tegra->dev, "failed to initialize timeout: %d\n", err); in tegra186_wdt_create()
287 err = devm_watchdog_register_device(tegra->dev, &wdt->base); in tegra186_wdt_create()
289 dev_err(tegra->dev, "failed to register WDT: %d\n", err); in tegra186_wdt_create()
302 hi = readl_relaxed(tegra->regs + TKETSC1); in tegra186_timer_tsc_read()
305 * The 56-bit value of the TSC is spread across two registers that are in tegra186_timer_tsc_read()
313 lo = readl_relaxed(tegra->regs + TKETSC0); in tegra186_timer_tsc_read()
314 hi = readl_relaxed(tegra->regs + TKETSC1); in tegra186_timer_tsc_read()
322 tegra->tsc.name = "tsc"; in tegra186_timer_tsc_init()
323 tegra->tsc.rating = 300; in tegra186_timer_tsc_init()
324 tegra->tsc.read = tegra186_timer_tsc_read; in tegra186_timer_tsc_init()
325 tegra->tsc.mask = CLOCKSOURCE_MASK(56); in tegra186_timer_tsc_init()
326 tegra->tsc.flags = CLOCK_SOURCE_IS_CONTINUOUS; in tegra186_timer_tsc_init()
328 return clocksource_register_hz(&tegra->tsc, 31250000); in tegra186_timer_tsc_init()
336 return readl_relaxed(tegra->regs + TKEOSC); in tegra186_timer_osc_read()
341 tegra->osc.name = "osc"; in tegra186_timer_osc_init()
342 tegra->osc.rating = 300; in tegra186_timer_osc_init()
343 tegra->osc.read = tegra186_timer_osc_read; in tegra186_timer_osc_init()
344 tegra->osc.mask = CLOCKSOURCE_MASK(32); in tegra186_timer_osc_init()
345 tegra->osc.flags = CLOCK_SOURCE_IS_CONTINUOUS; in tegra186_timer_osc_init()
347 return clocksource_register_hz(&tegra->osc, 38400000); in tegra186_timer_osc_init()
355 return readl_relaxed(tegra->regs + TKEUSEC); in tegra186_timer_usec_read()
360 tegra->usec.name = "usec"; in tegra186_timer_usec_init()
361 tegra->usec.rating = 300; in tegra186_timer_usec_init()
362 tegra->usec.read = tegra186_timer_usec_read; in tegra186_timer_usec_init()
363 tegra->usec.mask = CLOCKSOURCE_MASK(32); in tegra186_timer_usec_init()
364 tegra->usec.flags = CLOCK_SOURCE_IS_CONTINUOUS; in tegra186_timer_usec_init()
366 return clocksource_register_hz(&tegra->usec, USEC_PER_SEC); in tegra186_timer_usec_init()
373 if (watchdog_active(&tegra->wdt->base)) { in tegra186_timer_irq()
374 tegra186_wdt_disable(tegra->wdt); in tegra186_timer_irq()
375 tegra186_wdt_enable(tegra->wdt); in tegra186_timer_irq()
383 struct device *dev = &pdev->dev; in tegra186_timer_probe()
390 return -ENOMEM; in tegra186_timer_probe()
392 tegra->soc = of_device_get_match_data(dev); in tegra186_timer_probe()
394 tegra->dev = dev; in tegra186_timer_probe()
396 tegra->regs = devm_platform_ioremap_resource(pdev, 0); in tegra186_timer_probe()
397 if (IS_ERR(tegra->regs)) in tegra186_timer_probe()
398 return PTR_ERR(tegra->regs); in tegra186_timer_probe()
407 tegra->wdt = tegra186_wdt_create(tegra, 0); in tegra186_timer_probe()
408 if (IS_ERR(tegra->wdt)) { in tegra186_timer_probe()
409 err = PTR_ERR(tegra->wdt); in tegra186_timer_probe()
433 "tegra186-timer", tegra); in tegra186_timer_probe()
442 clocksource_unregister(&tegra->usec); in tegra186_timer_probe()
444 clocksource_unregister(&tegra->osc); in tegra186_timer_probe()
446 clocksource_unregister(&tegra->tsc); in tegra186_timer_probe()
454 clocksource_unregister(&tegra->usec); in tegra186_timer_remove()
455 clocksource_unregister(&tegra->osc); in tegra186_timer_remove()
456 clocksource_unregister(&tegra->tsc); in tegra186_timer_remove()
465 if (watchdog_active(&tegra->wdt->base)) in tegra186_timer_suspend()
466 tegra186_wdt_disable(tegra->wdt); in tegra186_timer_suspend()
475 if (watchdog_active(&tegra->wdt->base)) in tegra186_timer_resume()
476 tegra186_wdt_enable(tegra->wdt); in tegra186_timer_resume()
495 { .compatible = "nvidia,tegra186-timer", .data = &tegra186_timer },
496 { .compatible = "nvidia,tegra234-timer", .data = &tegra234_timer },
503 .name = "tegra186-timer",