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/Linux-v5.15/Documentation/devicetree/bindings/phy/
Dmediatek,xsphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek XS-PHY Controller Device Tree Bindings
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The XS-PHY controller supports physical layer functionality for USB3.1
18 ----------------------------------
45 pattern: "^xs-phy@[0-9a-f]+$"
49 - enum:
50 - mediatek,mt3611-xsphy
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Dmediatek,tphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller Device Tree Bindings
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
67 pattern: "^t-phy@[0-9a-f]+$"
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/Linux-v5.15/drivers/phy/mediatek/
Dphy-mtk-xsphy.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/phy/phy.h>
101 /* u2 eye diagram */
119 void __iomem *pbase = inst->port_base; in u2_phy_slew_rate_calibrate()
125 if (inst->eye_src) in u2_phy_slew_rate_calibrate()
168 tmp = xsphy->src_ref_clk * xsphy->src_coef; in u2_phy_slew_rate_calibrate()
175 dev_dbg(xsphy->dev, "phy.%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n", in u2_phy_slew_rate_calibrate()
176 inst->index, fm_out, calib_val, in u2_phy_slew_rate_calibrate()
177 xsphy->src_ref_clk, xsphy->src_coef); in u2_phy_slew_rate_calibrate()
194 void __iomem *pbase = inst->port_base; in u2_phy_instance_init()
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Dphy-mtk-tphy.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
21 /* version V1 sub-banks offset base address */
32 /* version V2/V3 sub-banks offset base address */
228 /* CDR Charge Pump P-path current adjustment */
254 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
266 /* I-path capacitance adjustment for Gen1 */
360 struct u2phy_banks *u2_banks = &instance->u2_banks; in hs_slew_rate_calibrate()
361 void __iomem *fmreg = u2_banks->fmreg; in hs_slew_rate_calibrate()
362 void __iomem *com = u2_banks->com; in hs_slew_rate_calibrate()
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/Linux-v5.15/drivers/phy/
Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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/Linux-v5.15/fs/nfs/
Dwrite.c1 // SPDX-License-Identifier: GPL-2.0-only
23 #include <linux/backing-dev.h>
94 INIT_LIST_HEAD(&p->pages); in nfs_commitdata_alloc()
110 p->rw_mode = FMODE_WRITE; in nfs_writehdr_alloc()
127 ioc->complete = complete; in nfs_io_completion_init()
128 ioc->data = data; in nfs_io_completion_init()
129 kref_init(&ioc->refcount); in nfs_io_completion_init()
136 ioc->complete(ioc->data); in nfs_io_completion_release()
143 kref_get(&ioc->refcount); in nfs_io_completion_get()
149 kref_put(&ioc->refcount, nfs_io_completion_release); in nfs_io_completion_put()
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/Linux-v5.15/drivers/gpu/drm/amd/display/dc/calcs/
Ddce_calcs.c38 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
42 * remain as-is as it provides us with a guarantee from HW that it is correct.
141 yclk[low] = vbios->low_yclk; in calculate_bandwidth()
142 yclk[mid] = vbios->mid_yclk; in calculate_bandwidth()
143 yclk[high] = vbios->high_yclk; in calculate_bandwidth()
144 sclk[s_low] = vbios->low_sclk; in calculate_bandwidth()
145 sclk[s_mid1] = vbios->mid1_sclk; in calculate_bandwidth()
146 sclk[s_mid2] = vbios->mid2_sclk; in calculate_bandwidth()
147 sclk[s_mid3] = vbios->mid3_sclk; in calculate_bandwidth()
148 sclk[s_mid4] = vbios->mid4_sclk; in calculate_bandwidth()
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/Linux-v5.15/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_dp.c47 link->ctx->logger
98 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) { in get_eq_training_aux_rd_interval()
99 /* DP 1.2 or later - retrieve delay through in get_eq_training_aux_rd_interval()
193 struct dpcd_caps *dpcd_caps = &link->dpcd_caps; in decide_eq_training_pattern()
198 if (link->is_dig_mapping_flexible && in decide_eq_training_pattern()
199 link->dc->res_pool->funcs->link_encs_assign) in decide_eq_training_pattern()
200 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link); in decide_eq_training_pattern()
202 link_enc = link->link_enc; in decide_eq_training_pattern()
204 features = &link_enc->features; in decide_eq_training_pattern()
206 if (features->flags.bits.IS_TPS3_CAPABLE) in decide_eq_training_pattern()
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/Linux-v5.15/drivers/net/ethernet/sfc/
Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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/Linux-v5.15/
DMAINTAINERS9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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