Lines Matching +full:eye +full:- +full:src
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller Device Tree Bindings
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
67 pattern: "^t-phy@[0-9a-f]+$"
71 - items:
72 - enum:
73 - mediatek,mt2701-tphy
74 - mediatek,mt7623-tphy
75 - mediatek,mt7622-tphy
76 - mediatek,mt8516-tphy
77 - const: mediatek,generic-tphy-v1
78 - items:
79 - enum:
80 - mediatek,mt2712-tphy
81 - mediatek,mt7629-tphy
82 - mediatek,mt8183-tphy
83 - const: mediatek,generic-tphy-v2
84 - items:
85 - enum:
86 - mediatek,mt8195-tphy
87 - const: mediatek,generic-tphy-v3
88 - const: mediatek,mt2701-u3phy
90 - const: mediatek,mt2712-u3phy
92 - const: mediatek,mt8173-u3phy
97 It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
98 T-PHY V2/V3, such as mt2712.
101 "#address-cells":
104 "#size-cells":
107 # Used with non-empty value if optional 'reg' is not provided.
109 # (child-bus-address, parent-bus-address, length).
112 mediatek,src-ref-clk-mhz:
117 mediatek,src-coef:
125 "^(usb|pcie|sata)-phy@[0-9a-f]+$":
128 A sub-node is required for each port the controller provides.
139 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
140 - description: Reference clock of analog phy
145 clock-names:
148 - const: ref
149 - const: da_ref
151 "#phy-cells":
156 - description: The PHY type
158 - PHY_TYPE_USB2
159 - PHY_TYPE_USB3
160 - PHY_TYPE_PCIE
161 - PHY_TYPE_SATA
164 mediatek,eye-src:
171 mediatek,eye-vrt:
178 mediatek,eye-term:
204 mediatek,syscon-type:
205 $ref: /schemas/types.yaml#/definitions/phandle-array
212 - description:
214 - description:
216 - description:
221 - reg
222 - "#phy-cells"
227 - compatible
228 - "#address-cells"
229 - "#size-cells"
230 - ranges
235 - |
236 #include <dt-bindings/clock/mt8173-clk.h>
237 #include <dt-bindings/interrupt-controller/arm-gic.h>
238 #include <dt-bindings/interrupt-controller/irq.h>
239 #include <dt-bindings/phy/phy.h>
241 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
243 reg-names = "mac", "ippc";
249 clock-names = "sys_ck";
252 t-phy@11290000 {
253 compatible = "mediatek,mt8173-u3phy";
255 #address-cells = <1>;
256 #size-cells = <1>;
259 u2port0: usb-phy@11290800 {
262 clock-names = "ref", "da_ref";
263 #phy-cells = <1>;
266 u3port0: usb-phy@11290900 {
269 clock-names = "ref";
270 #phy-cells = <1>;
273 u2port1: usb-phy@11291000 {
275 #phy-cells = <1>;