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/Linux-v5.15/sound/soc/atmel/
Datmel-pcm.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * at91-pcm.h - ALSA PCM interface for the Atmel AT91 SoC.
10 * Based on at91-pcm. by:
14 * Based on pxa2xx-pcm.c by:
24 #include <linux/atmel-ssc.h>
40 u32 ssc_enable; /* SSC recv/trans enable */
41 u32 ssc_disable; /* SSC recv/trans disable */
42 u32 ssc_error; /* SSC error conditions */
43 u32 ssc_endx; /* SSC ENDTX or ENDRX */
44 u32 ssc_endbuf; /* SSC TXBUFE or RXBUFF */
[all …]
Datmel_ssc_dai.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * atmel_ssc_dai.c -- ALSA SoC ATMEL SSC Audio Layer Platform driver
11 * Based on at91-ssc.c by
25 #include <linux/atmel-ssc.h>
32 #include "atmel-pcm.h"
39 * SSC PDC registers required by the PCM DMA engine.
56 * SSC & PDC status bits for transmit and receive.
136 * SSC interrupt handler. Passes PDC interrupts to the DMA
147 ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR) in atmel_ssc_interrupt()
148 & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR); in atmel_ssc_interrupt()
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/Linux-v5.15/include/linux/
Datmel-ssc.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 void ssc_free(struct ssc_device *ssc);
30 /* SSC register offsets */
32 /* SSC Control Register */
45 /* SSC Clock Mode Register */
50 /* SSC Receive Clock Mode Register */
69 /* SSC Receive Frame Mode Register */
92 /* SSC Transmit Clock Mode Register */
109 /* SSC Transmit Frame Mode Register */
134 /* SSC Receive Hold Register */
[all …]
/Linux-v5.15/include/linux/clk/
Dti.h18 #include <linux/clk-provider.h>
22 * struct clk_omap_reg - OMAP register declaration
34 * struct dpll_data - DPLL registers and integration data
48 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
50 * @min_divider: minimum valid non-bypass divider value (actual)
51 * @max_divider: maximum valid non-bypass divider value (actual)
61 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
63 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
66 * @ssc_deltam_reg: register containing the DPLL SSC frequency spreading
67 * @ssc_modfreq_reg: register containing the DPLL SSC modulation frequency
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/Linux-v5.15/drivers/mmc/host/
Dsdhci-pci-gli.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Version: v0.9.0 (2019-08-08)
16 #include "sdhci-pci.h"
245 /* enable tuning parameters control */ in gli_set_9750()
302 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
315 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
317 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
318 return -ETIMEDOUT; in __sdhci_execute_tuning_9750()
322 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
325 return -EAGAIN; in __sdhci_execute_tuning_9750()
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/Linux-v5.15/Documentation/devicetree/bindings/clock/ti/
Ddpll.txt3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped DPLL with usually two selectable input clocks
11 sub-types, which effectively result in slightly different setup
14 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be one of:
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
22 "ti,omap4-dpll-clock",
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/Linux-v5.15/drivers/scsi/isci/
Dprobe_roms.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
80 * This field specifies the NOTIFY (ENABLE SPIN UP) primitive
103 * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
104 * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
105 * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
228 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
229 * NOTE: Default SSC Modulation Frequency is 31.5KHz.
234 * NOTE: Max spread for SATA is +0 / -5000 PPM.
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/Linux-v5.15/drivers/scsi/mvsas/
Dmv_94xx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
45 MVS_STP_REG_SET_0 = 0x118, /* STP/SATA Register Set Enable */
61 MVS_INT_MASK = 0x154, /* Central int enable */
66 MVS_NON_NCQ_ERR_0 = 0x168, /* SRS Non-specific NCQ Error */
72 /* ports 1-3 follow after this */
75 /* ports 5-7 follow after this */
77 MVS_P4_INT_MASK = 0x1A4, /* Port4 interrupt enable mask */
79 /* ports 1-3 follow after this */
81 /* ports 5-7 follow after this */
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/Linux-v5.15/Documentation/devicetree/bindings/phy/
Drenesas,usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
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Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
23 - ti,j721e-serdes-10g
25 '#address-cells':
28 '#size-cells':
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Dbrcm,sata-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/brcm,sata-phy.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Florian Fainelli <f.fainelli@gmail.com>
14 pattern: "^sata[-|_]phy(@.*)?$"
18 - items:
19 - enum:
20 - brcm,bcm7216-sata-phy
21 - brcm,bcm7425-sata-phy
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/Linux-v5.15/sound/spi/
Dat73c213.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for AT73C213 16-bit stereo DAC connected to Atmel SSC
5 * Copyright (C) 2006-2007 Atmel Norway
14 #include <linux/dma-mapping.h>
27 #include <linux/atmel-ssc.h>
41 0x00, /* 00 - CTRL */
42 0x05, /* 01 - LLIG */
43 0x05, /* 02 - RLIG */
44 0x08, /* 03 - LPMG */
45 0x08, /* 04 - RPMG */
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/Linux-v5.15/drivers/spi/
Dspi-st-ssc4.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014 STMicroelectronics Limited
26 /* SSC registers */
34 /* SSC Control */
49 /* SSC Interrupt Enable */
55 /* SSC SPI Controller */
60 /* SSC SPI current transaction */
75 if (spi_st->words_remaining > FIFO_SIZE) in ssc_write_tx_fifo()
78 count = spi_st->words_remaining; in ssc_write_tx_fifo()
81 if (spi_st->tx_ptr) { in ssc_write_tx_fifo()
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/Linux-v5.15/include/linux/phy/
Dphy-dp.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
51 * Pre-emphasis levels, as specified by DisplayPort specification, to be
59 * @ssc:
61 * Flag indicating, whether or not to enable spread-spectrum clocking.
64 u8 ssc : 1; member
69 * Flag indicating, whether or not reconfigure link rate and SSC to
88 * and pre-emphasis to requested values. Only lanes specified
/Linux-v5.15/drivers/phy/cadence/
Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
12 #include <linux/clk-provider.h>
239 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
393 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_write()
395 writew(val, ctx->base + offset); in cdns_regmap_write()
403 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_read()
405 *val = readw(ctx->base + offset); in cdns_regmap_read()
415 writel(val, ctx->base + offset); in cdns_regmap_dptx_write()
[all …]
/Linux-v5.15/drivers/phy/xilinx/
Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
61 /* PLL SSC step size offsets */
70 /* SSC step size parameters */
170 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
173 * @steps: number of steps of SSC (Spread Spectrum Clock)
184 * struct xpsgtr_phy - representation of a lane
[all …]
/Linux-v5.15/drivers/i2c/busses/
Di2c-st.c1 // SPDX-License-Identifier: GPL-2.0-only
23 /* SSC registers */
47 /* SSC Control */
62 /* SSC Interrupt Enable */
76 /* SSC Status */
93 /* SSC I2C Control */
103 /* SSC Tx FIFO Status */
106 /* SSC Rx FIFO Status */
109 /* SSC Clear bit operation */
116 /* SSC Clock Prescaler */
[all …]
/Linux-v5.15/drivers/phy/st/
Dphy-miphy28lp.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <dt-bindings/phy/phy.h>
170 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
172 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
210 bool ssc; member
237 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
366 void __iomem *base = miphy_phy->base; in miphy28lp_set_reset()
377 /* Bringing the MIPHY-CPU registers out of reset */ in miphy28lp_set_reset()
378 if (miphy_phy->type == PHY_TYPE_PCIE) { in miphy28lp_set_reset()
390 void __iomem *base = miphy_phy->base; in miphy28lp_pll_calibration()
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/Linux-v5.15/Documentation/devicetree/bindings/pci/
Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm4908-pcie
18 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
19 - brcm,bcm7278-pcie # Broadcom 7278 Arm
[all …]
/Linux-v5.15/drivers/phy/ralink/
Dphy-mt7621-pci.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/phy/phy.h>
67 * struct mt7621_pci_phy - Mt7621 Pcie PHY core
99 regmap_read(phy->regmap, reg, &val); in mt7621_phy_rmw()
102 regmap_write(phy->regmap, reg, val); in mt7621_phy_rmw()
110 if (phy->has_dual_port) { in mt7621_bypass_pipe_rst()
120 struct device *dev = phy->dev; in mt7621_set_phy_for_ssc()
123 clk_rate = clk_get_rate(phy->sys_clk); in mt7621_set_phy_for_ssc()
125 return -EINVAL; in mt7621_set_phy_for_ssc()
127 /* Set PCIe Port PHY to disable SSC */ in mt7621_set_phy_for_ssc()
[all …]
/Linux-v5.15/drivers/phy/broadcom/
Dphy-bcm-ns-usb3.c1 // SPDX-License-Identifier: GPL-2.0-only
58 .compatible = "brcm,ns-ax-usb3-phy",
62 .compatible = "brcm,ns-bx-usb3-phy",
94 writel(0, usb3->dmp + BCMA_RESET_CTL); in bcm_ns_usb3_phy_init_ns_bx()
96 /* PLL frequency monitor enable */ in bcm_ns_usb3_phy_init_ns_bx()
113 /* Enabling SSC */ in bcm_ns_usb3_phy_init_ns_bx()
135 /* Enable SSC */ in bcm_ns_usb3_phy_init_ns_ax()
144 writel(0, usb3->dmp + BCMA_RESET_CTL); in bcm_ns_usb3_phy_init_ns_ax()
155 writel(BCMA_RESET_CTL_RESET, usb3->dmp + BCMA_RESET_CTL); in bcm_ns_usb3_phy_init()
157 switch (usb3->family) { in bcm_ns_usb3_phy_init()
[all …]
/Linux-v5.15/drivers/misc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
27 See Documentation/misc-devices/ad525x_dpot.rst for the
40 module will be called ad525x_dpot-i2c.
51 module will be called ad525x_dpot-spi.
65 This option enables device driver support for in-band access to the
78 website <https://www-03.ibm.com/systems/info/x86servers/serverproven/compat/us/>
147 tristate "Device driver for Atmel SSC peripheral"
151 Serial Communication peripheral (SSC).
153 The SSC peripheral supports a wide variety of serial frame based
180 tristate "CS5535/CS5536 Geode Multi-Function General Purpose Timer (MFGPT) support"
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/Linux-v5.15/drivers/pci/controller/
Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
25 #include <linux/pci-ecam.h>
35 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
173 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
174 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
175 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
285 bool ssc; member
302 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
310 return (log2_in - 12) + 0x1c; in brcm_pcie_encode_ibar_size()
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dsama5d3xmb.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
21 bus-width = <4>;
22 cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>;
31 spi-max-frequency = <50000000>;
36 ssc0: ssc@f0008000 {
37 atmel,clk-from-rk-pin;
43 * can not enable audio when i2c0 disabled
[all …]
Dsama5d3xmb_cmp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama5d3xmb_cmp.dts - Device Tree file for SAMA5D3x CMP mother board
10 compatible = "atmel,sama5d3xmb-cmp", "atmel,sama5d3xcm-cmp", "atmel,sama5d3", "atmel,sama5";
15 pinctrl-names = "default";
16 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
20 bus-width = <4>;
21 cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>;
30 spi-max-frequency = <50000000>;
35 ssc0: ssc@f0008000 {
36 atmel,clk-from-rk-pin;
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