Searched +full:enable +full:- +full:bias +full:- +full:control (Results 1 – 25 of 295) sorted by relevance
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| /Linux-v6.1/Documentation/devicetree/bindings/pinctrl/ |
| D | sprd,pinctrl.txt | 5 The first block comprises some global control registers, and each
8 pad driving level, system control select and so on ("domain pad
11 slect 3.0v, then the pin can output 3.0v. "system control" is used
16 of them, so we can not make every Spreadtrum-special configuration
18 global configuration in future. Then we add one "sprd,control" to
19 set these various global control configuration, and we need use
23 bits in one global control register as one pin, thus we should
35 - input-enable
36 - input-disable
37 - output-high
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| D | sprd,sc9860-pinctrl.txt | 7 - compatible: Must be "sprd,sc9860-pinctrl".
8 - reg: The register address of pin controller device.
9 - pins : An array of strings, each string containing the name of a pin.
12 - function: A string containing the name of the function, values must be
14 - drive-strength: Drive strength in mA. Supported values: 2, 4, 6, 8, 10,
16 - input-schmitt-disable: Enable schmitt-trigger mode.
17 - input-schmitt-enable: Disable schmitt-trigger mode.
18 - bias-disable: Disable pin bias.
19 - bias-pull-down: Pull down on pin.
20 - bias-pull-up: Pull up on pin. Supported values: 20000 for pull-up resistor
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| D | pinctrl-single.txt | 1 One-register-per-pin type device tree based pinctrl driver
4 - compatible : "pinctrl-single" or "pinconf-single".
5 "pinctrl-single" means that pinconf isn't supported.
6 "pinconf-single" means that generic pinconf is supported.
8 - reg : offset and length of the register set for the mux registers
10 - #pinctrl-cells : number of cells in addition to the index, set to 1
11 or 2 for pinctrl-single,pins and set to 2 for pinctrl-single,bits
13 - pinctrl-single,register-width : pinmux register access width in bits
15 - pinctrl-single,function-mask : mask of allowed pinmux function bits
19 - pinctrl-single,function-off : function off mode for disabled state if
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| D | brcm,nsp-gpio.txt | 4 - compatible:
5 Must be "brcm,nsp-gpio-a"
7 - reg:
9 GPIO base, IO control registers
11 - #gpio-cells:
16 - gpio-controller:
19 - ngpios:
23 - interrupts:
26 - interrupt-controller:
29 - gpio-ranges:
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| D | pincfg-node.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pincfg-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
14 and generic. Pin control bindings should use the properties defined below
21 bias-disable:
23 description: disable any pin bias
25 bias-high-impedance:
27 description: high impedance mode ("third-state", "floating")
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| D | mediatek,mt65xx-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
13 The Mediatek's Pin controller is used to control SoC pins.
18 - mediatek,mt2701-pinctrl
19 - mediatek,mt2712-pinctrl
20 - mediatek,mt6397-pinctrl
21 - mediatek,mt7623-pinctrl
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| D | actions,s500-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/actions,s500-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11 - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
16 pinctrl-bindings.txt in this directory for common binding part and usage.
20 const: actions,s500-pinctrl
24 - description: GPIO Output + GPIO Input + GPIO Data
25 - description: Multiplexing Control
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| D | brcm,iproc-gpio.txt | 5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
23 - reg:
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| D | intel,pinctrl-thunderbay.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-thunderbay.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
13 Intel Thunder Bay SoC integrates a pin controller which enables control
19 const: intel,thunderbay-pinctrl
24 gpio-controller: true
26 '#gpio-cells':
29 gpio-ranges:
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| D | canaan,k210-fpioa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/canaan,k210-fpioa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Damien Le Moal <damien.lemoal@wdc.com>
16 a per-pin basis.
20 const: canaan,k210-fpioa
29 - description: Controller reference clock source
30 - description: APB interface clock source
32 clock-names:
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| D | intel,pinctrl-keembay.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
13 Intel Keem Bay SoC integrates a pin controller which enables control
19 const: intel,keembay-pinctrl
24 gpio-controller: true
26 '#gpio-cells':
39 interrupt-controller: true
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| D | pinctrl-mt8195.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8195.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
13 The Mediatek's Pin controller is used to control SoC pins.
17 const: mediatek,mt8195-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
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| D | pinctrl-mt8192.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
13 The Mediatek's Pin controller is used to control SoC pins.
17 const: mediatek,mt8192-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
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| D | pinctrl-mt8186.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8186.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
13 The Mediatek's Pin controller is used to control SoC pins.
17 const: mediatek,mt8186-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
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| /Linux-v6.1/Documentation/devicetree/bindings/mfd/ |
| D | as3722.txt | 4 -------------------
5 - compatible: Must be "ams,as3722".
6 - reg: I2C device address.
7 - interrupt-controller: AS3722 has internal interrupt controller which takes the
8 interrupt request from internal sub-blocks like RTC, regulators, GPIOs as well
10 - #interrupt-cells: Should be set to 2 for IRQ number and flags.
12 of AS3722 are defined at dt-bindings/mfd/as3722.h
14 interrupts.txt, using dt-bindings/irq.
17 --------------------
18 - ams,enable-internal-int-pullup: Boolean property, to enable internal pullup on
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| /Linux-v6.1/Documentation/devicetree/bindings/regulator/ |
| D | maxim,max8973.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: regulator.yaml#
18 - maxim,max8973
19 - maxim,max77621
21 junction-warn-millicelsius:
30 maxim,dvs-gpio:
35 maxim,dvs-default-state:
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| D | ti-abb-regulator.txt | 1 Adaptive Body Bias(ABB) SoC internal LDO regulator for Texas Instruments SoCs
4 - compatible: Should be one of:
5 - "ti,abb-v1" for older SoCs like OMAP3
6 - "ti,abb-v2" for newer SoCs like OMAP4, OMAP5
7 - "ti,abb-v3" for a generic definition where setup and control registers are
9 - reg: Address and length of the register set for the device. It contains
10 the information of registers in the same order as described by reg-names
11 - reg-names: Should contain the reg names
12 - "base-address" - contains base address of ABB module (ti,abb-v1,ti,abb-v2)
13 - "control-address" - contains control register address of ABB module (ti,abb-v3)
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| D | richtek,rt4801-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rt4801-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Richtek RT4801 Display Bias regulators
10 - ChiYuan Huang <cy_huang@richtek.com>
18 https://www.richtek.com/assets/product_file/RT4801H/DS4801H-00.pdf
23 - richtek,rt4801
28 enable-gpios:
29 description: GPIOs to use to enable DSVP/DSVN regulator.
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| /Linux-v6.1/Documentation/devicetree/bindings/display/tilcdc/ |
| D | panel.txt | 1 Device-Tree bindings for tilcdc DRM generic panel output driver
4 - compatible: value should be "ti,tilcdc,panel".
5 - panel-info: configuration info to configure LCDC correctly for the panel
6 - ac-bias: AC Bias Pin Frequency
7 - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
8 - dma-burst-sz: DMA burst size
9 - bpp: Bits per pixel
10 - fdd: FIFO DMA Request Delay
11 - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
12 - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
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| /Linux-v6.1/sound/soc/codecs/ |
| D | cs53l30.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
19 #define CS53L30_PWRCTL 0x06 /* Power Control. */
20 #define CS53L30_MCLKCTL 0x07 /* MCLK Control. */
21 #define CS53L30_INT_SR_CTL 0x08 /* Internal Sample Rate Control. */
22 #define CS53L30_MICBIAS_CTL 0x0A /* Mic Bias Control. */
23 #define CS53L30_ASPCFG_CTL 0x0C /* ASP Config Control. */
24 #define CS53L30_ASP_CTL1 0x0D /* ASP1 Control. */
25 #define CS53L30_ASP_TDMTX_CTL1 0x0E /* ASP1 TDM TX Control 1 */
26 #define CS53L30_ASP_TDMTX_CTL2 0x0F /* ASP1 TDM TX Control 2 */
27 #define CS53L30_ASP_TDMTX_CTL3 0x10 /* ASP1 TDM TX Control 3 */
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| D | wm8737.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * wm8737.c -- WM8523 ALSA SoC Audio driver
41 * R0 (0x00) - Left PGA volume
47 #define WM8737_LINVOL_MASK 0x00FF /* LINVOL - [7:0] */
48 #define WM8737_LINVOL_SHIFT 0 /* LINVOL - [7:0] */
49 #define WM8737_LINVOL_WIDTH 8 /* LINVOL - [7:0] */
52 * R1 (0x01) - Right PGA volume
58 #define WM8737_RINVOL_MASK 0x00FF /* RINVOL - [7:0] */
59 #define WM8737_RINVOL_SHIFT 0 /* RINVOL - [7:0] */
60 #define WM8737_RINVOL_WIDTH 8 /* RINVOL - [7:0] */
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| /Linux-v6.1/Documentation/devicetree/bindings/leds/ |
| D | leds-lm36274.txt | 1 * Texas Instruments LM36274 4-Channel LCD Backlight Driver w/Integrated Bias
3 The LM36274 is an integrated four-channel WLED driver and LCD bias supply.
4 The backlight boost provides the power to bias four parallel LED strings with
5 up to 29V total output voltage. The 11-bit LED current is programmable via
9 Documentation/devicetree/bindings/mfd/ti-lmu.txt
12 Documentation/devicetree/bindings/regulator/lm363x-regulator.txt
15 - compatible:
16 "ti,lm36274-backlight"
17 - reg : 0
18 - #address-cells : 1
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| /Linux-v6.1/arch/arm/boot/dts/ |
| D | nuvoton-npcm730-kudo.dts | 1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
5 #include "nuvoton-npcm730.dtsi"
7 #include <dt-bindings/gpio/gpio.h>
41 stdout-path = &serial3;
48 iio-hwmon {
49 compatible = "iio-hwmon";
50 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
55 compatible = "nuvoton,npcm750-jtag-master";
56 #address-cells = <1>;
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| /Linux-v6.1/sound/pci/cs5535audio/ |
| D | cs5535audio_olpc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * OLPC XO-1 additional sound features
6 * Copyright © 2007-2008 Andres Salomon <dilinger@debian.org>
10 #include <sound/control.h>
17 #define DRV_NAME "cs5535audio-olpc"
35 dev_err(ac97->bus->card->dev, in olpc_analog_input()
36 "setting High Pass Filter - %d\n", err); in olpc_analog_input()
45 * OLPC XO-1's V_REFOUT is a mic bias enable.
58 dev_err(ac97->bus->card->dev, "setting MIC Bias - %d\n", err); in olpc_mic_bias()
64 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; in olpc_dc_info()
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| /Linux-v6.1/arch/arm64/boot/dts/qcom/ |
| D | sc7280-herobrine.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
16 #include <dt-bindings/input/gpio-keys.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/leds/common.h>
20 #include "sc7280-qcard.dtsi"
21 #include "sc7280-chrome-common.dtsi"
25 stdout-path = "serial0:115200n8";
38 ppvar_sys: ppvar-sys-regulator {
39 compatible = "regulator-fixed";
40 regulator-name = "ppvar_sys";
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