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/Linux-v6.1/Documentation/devicetree/bindings/media/i2c/
Dst,st-mipid02.txt1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
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/Linux-v6.1/Documentation/devicetree/bindings/display/bridge/
Dtoshiba,tc358775.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinay Simha BN <simhavcs@gmail.com>
15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
30 vdd-supply:
33 vddio-supply:
36 stby-gpios:
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Dti,sn65dsi83.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
14 to 1x Single-link LVDS
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
17 to 1x Dual-link or 2x Single-link LVDS
23 - ti,sn65dsi83
24 - ti,sn65dsi84
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/Linux-v6.1/drivers/net/dsa/b53/
Db53_serdes.c1 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
42 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
47 WARN_ON(lane > 1); in b53_serdes_set_lane()
50 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
54 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
57 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
61 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
64 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
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/Linux-v6.1/include/linux/phy/
Dphy-lvds.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_lvds - LVDS configuration set
11 * @bits_per_lane_and_dclk_cycle: Number of bits per lane per differential
16 * data lanes, starting from lane 0,
20 * phy to support dual link transmission,
/Linux-v6.1/Documentation/devicetree/bindings/connector/
Dusb-connector.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/connector/usb-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
20 - enum:
21 - usb-a-connector
22 - usb-b-connector
23 - usb-c-connector
25 - items:
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/Linux-v6.1/drivers/phy/intel/
Dphy-intel-lgm-combo.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Combo-PHY driver
5 * Copyright (C) 2019-2020 Intel Corporation.
20 #include <dt-bindings/phy/phy.h>
33 #define CR_ADDR(addr, lane) (((addr) + (lane) * 0x100) << 2) argument
37 #define COMBO_PHY_ID(x) ((x)->parent->id)
38 #define PHY_ID(x) ((x)->id)
107 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_iphy_enable()
108 u32 mask = BIT(cbphy->phy_mode * 2 + iphy->id); in intel_cbphy_iphy_enable()
114 return regmap_update_bits(cbphy->hsiocfg, REG_CLK_DISABLE(cbphy->bid), in intel_cbphy_iphy_enable()
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/Linux-v6.1/drivers/gpu/drm/
Ddrm_of.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/media-bus-format.h>
24 * drm_of_crtc_port_mask - find the mask of a registered CRTC by port OF node
38 if (tmp->port == port) in drm_of_crtc_port_mask()
49 * drm_of_find_possible_crtcs - find the possible CRTCs for an encoder port
82 * drm_of_component_match_add - Add a component helper OF node match rule
100 * drm_of_component_probe - Generic probe function for a component based master
120 if (!dev->of_node) in drm_of_component_probe()
121 return -EINVAL; in drm_of_component_probe()
128 port = of_parse_phandle(dev->of_node, "ports", i); in drm_of_component_probe()
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/Linux-v6.1/drivers/gpu/drm/bridge/
Dtc358775.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/media-bus-format.h>
36 /* DSI D-PHY Layer Registers */
37 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
38 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
39 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
40 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
41 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
42 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
44 #define CLW_CNTRL 0x0040 /* Clock Lane Control */
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Dtc358762.c1 // SPDX-License-Identifier: GPL-2.0
34 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
35 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
39 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
40 #define DSI_LANEENABLE 0x0210 /* Enables each lane */
56 /* Lane enable PPI and DSI register bits */
72 int ret = ctx->error; in tc358762_clear_error()
74 ctx->error = 0; in tc358762_clear_error()
80 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in tc358762_write()
84 if (ctx->error) in tc358762_write()
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/Linux-v6.1/drivers/gpu/drm/i915/display/
Dicl_dsi.c69 drm_err(&dev_priv->drm, "DSI header credits not released\n"); in wait_for_header_credits()
81 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); in wait_for_payload_credits()
98 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in wait_for_cmds_dispatched_to_panel()
106 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
113 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
114 dsi = intel_dsi->dsi_hosts[port]->device; in wait_for_cmds_dispatched_to_panel()
115 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in wait_for_cmds_dispatched_to_panel()
116 dsi->channel = 0; in wait_for_cmds_dispatched_to_panel()
119 drm_err(&dev_priv->drm, in wait_for_cmds_dispatched_to_panel()
124 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
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Dintel_dpio_phy.c2 * Copyright © 2014-2016 Intel Corporation
42 * IOSF-SB port.
45 * houses a common lane part which contains the PLL and other common
46 * logic. CH0 common lane also contains the IOSF-SB logic for the
56 * each spline is made up of one Physical Access Coding Sub-Layer
61 * Additionally the PHY also contains an AUX lane with AUX blocks
67 * Generally on VLV/CHV the common lane corresponds to the pipe and
70 * For dual channel PHY (VLV/CHV):
99 * Dual channel PHY (VLV/CHV/BXT)
100 * ---------------------------------
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/Linux-v6.1/drivers/phy/qualcomm/
Dphy-qcom-qmp-ufs.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp.h"
46 * if yes, then offset gives index in the reg-layout
51 * for cases when second lane needs different values
78 /* set of registers with offsets different per-PHY */
534 /* struct qmp_phy_cfg - per-PHY initialization config */
538 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
568 * struct qmp_phy - per-lane phy descriptor
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/Linux-v6.1/drivers/ufs/host/
Dtc-dwc-g210.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
15 #include "ufshcd-dwc.h"
16 #include "ufshci-dwc.h"
17 #include "tc-dwc-g210.h"
21 * This function configures Synopsys TC specific atributes (40-bit RMMI)
24 * Returns 0 on success or non-zero value on failure
85 * This function configures Synopsys TC 20-bit RMMI Lane 0
88 * Returns 0 on success or non-zero value on failure
138 * This function configures Synopsys TC 20-bit RMMI Lane 1
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/Linux-v6.1/drivers/thunderbolt/
Dswitch.c1 // SPDX-License-Identifier: GPL-2.0
3 * Thunderbolt driver - switch/port utility functions
11 #include <linux/nvmem-provider.h>
30 MODULE_PARM_DESC(clx, "allow low power states on the high-speed lanes (default: true)");
45 if (uuid_equal(&st->uuid, sw->uuid)) in __nvm_get_auth_status()
60 *status = st ? st->status : 0; in nvm_get_auth_status()
67 if (WARN_ON(!sw->uuid)) in nvm_set_auth_status()
78 memcpy(&st->uuid, sw->uuid, sizeof(st->uuid)); in nvm_set_auth_status()
79 INIT_LIST_HEAD(&st->list); in nvm_set_auth_status()
80 list_add_tail(&st->list, &nvm_auth_status_cache); in nvm_set_auth_status()
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/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dintel,combo-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dilip Kota <eswara.kota@linux.intel.com>
18 pattern: "combophy(@.*|-[0-9a-f])*$"
22 - const: intel,combophy-lgm
23 - const: intel,combo-phy
30 - description: ComboPhy core registers
31 - description: PCIe app core control registers
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/Linux-v6.1/drivers/gpu/drm/amd/display/include/
Dgrph_object_ctrl_defs.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
179 uint32_t dp_phy_ref_clk; /* in KHz - DCE12 only */
180 uint32_t i2c_engine_ref_clk; /* in KHz - DCE12 only */
242 uint8_t lane0:2; /* Mapping for lane 0 */
243 uint8_t lane1:2; /* Mapping for lane 1 */
244 uint8_t lane2:2; /* Mapping for lane 2 */
245 uint8_t lane3:2; /* Mapping for lane 3 */
263 /* Secondary transmitter configuration for Dual-link DVI */
423 * DFS-bypass flag
431 INVALID_BACKLIGHT = -1
/Linux-v6.1/drivers/net/pcs/
Dpcs-lynx.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <linux/pcs-lynx.h>
38 #define lynx_to_phylink_pcs(lynx) (&(lynx)->pcs)
44 return lynx->mdio; in lynx_get_mdio_device()
51 struct mii_bus *bus = pcs->bus; in lynx_pcs_get_state_usxgmii()
52 int addr = pcs->addr; in lynx_pcs_get_state_usxgmii()
59 state->link = !!(status & MDIO_STAT1_LSTATUS); in lynx_pcs_get_state_usxgmii()
60 state->an_complete = !!(status & MDIO_AN_STAT1_COMPLETE); in lynx_pcs_get_state_usxgmii()
61 if (!state->link || !state->an_complete) in lynx_pcs_get_state_usxgmii()
79 state->link = false; in lynx_pcs_get_state_2500basex()
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/Linux-v6.1/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
12 - Jitao Shi <jitao.shi@mediatek.com>
13 - Xinlei Lee <xinlei.lee@mediatek.com>
17 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
21 - $ref: /schemas/display/dsi-controller.yaml#
26 - mediatek,mt2701-dsi
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/Linux-v6.1/drivers/gpu/drm/bridge/synopsys/
Ddw-mipi-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
193 #define N_LANES(n) (((n) - 1) & 0x3)
249 unsigned int lane_mbps; /* per lane */
265 struct dw_mipi_dsi *master; /* dual-dsi master ptr */
266 struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */
276 return dsi->slave || dsi->master; in dw_mipi_is_dual_mode()
304 writel(val, dsi->base + reg); in dsi_write()
309 return readl(dsi->base + reg); in dsi_read()
316 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; in dw_mipi_dsi_host_attach()
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/Linux-v6.1/Documentation/ABI/testing/
Dsysfs-bus-usb10 This allows to avoid side-effects with drivers
28 drivers, non-authorized one are not. By default, wired
42 A devices's CDID, as 16 space-separated hex octets.
53 space-separated hex octets.
67 Contact: linux-usb@vger.kernel.org
101 What: /sys/bus/usb-serial/drivers/.../new_id
103 Contact: linux-usb@vger.kernel.org
106 extra bus folder "usb-serial" in sysfs; apart from that
131 If CONFIG_PM is set and a USB 2.0 lpm-capable device is plugged
147 If CONFIG_PM is set and a USB 3.0 lpm-capable device is plugged
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/Linux-v6.1/drivers/net/dsa/mv88e6xxx/
Dchip.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Marvell 88E6xxx Ethernet switch single-chip definition
28 /* PVT limits for 4-bit port and 5-bit switch */
107 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level
146 * ports 2-4 are not routet to pins.
149 /* Multi-chip Addressing Mode.
151 * when it is non-zero, and use indirect access to internal registers.
154 /* Dual-chip Addressing Mode
332 /* Handles automatic disabling and re-enabling of the PHY
402 /* Per-port timestamping resources. */
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/Linux-v6.1/drivers/gpu/drm/display/
Ddrm_dp_helper.c75 return link_status[r - DP_LANE0_1_STATUS]; in dp_link_status()
79 int lane) in dp_get_lane_status() argument
81 int i = DP_LANE0_1_STATUS + (lane >> 1); in dp_get_lane_status()
82 int s = (lane & 1) * 4; in dp_get_lane_status()
93 int lane; in drm_dp_channel_eq_ok() local
99 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
100 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_channel_eq_ok()
111 int lane; in drm_dp_clock_recovery_ok() local
114 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
115 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_clock_recovery_ok()
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/Linux-v6.1/drivers/phy/rockchip/
Dphy-rockchip-dphy-rx0.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 * chromeos-4.4 branch.
14 * Jacob Chen <jacob2.chen@rock-chips.com>
15 * Shunqian Zheng <zhengsq@rock-chips.com>
26 #include <linux/phy/phy-mipi-dphy.h>
65 "dphy-ref",
66 "dphy-cfg",
111 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
163 const struct dphy_reg *reg = &priv->drv_data->regs[index]; in rk_dphy_write_grf()
165 unsigned int val = (value << reg->shift) | in rk_dphy_write_grf()
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/Linux-v6.1/arch/arm/boot/dts/
Dlpc4350-hitex-eval.dts6 * This code is released using a dual license strategy: BSD/GPL
9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
33 stdout-path = &uart0;
42 compatible = "gpio-keys-polled";
43 poll-interval = <100>;
97 compatible = "gpio-leds";
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