Lines Matching +full:dual +full:- +full:lane
1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/media-bus-format.h>
36 /* DSI D-PHY Layer Registers */
37 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
38 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
39 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
40 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
41 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
42 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
44 #define CLW_CNTRL 0x0040 /* Clock Lane Control */
45 #define D0W_CNTRL 0x0044 /* Data Lane 0 Control */
46 #define D1W_CNTRL 0x0048 /* Data Lane 1 Control */
47 #define D2W_CNTRL 0x004C /* Data Lane 2 Control */
48 #define D3W_CNTRL 0x0050 /* Data Lane 3 Control */
52 #define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */
58 #define PPI_LANEENABLE 0x0134 /* Enables each lane at the PPI layer. */
62 #define PPI_CLS_ATMR 0x0140 /* Delay for Clock Lane in LPRX */
63 #define PPI_D0S_ATMR 0x0144 /* Delay for Data Lane 0 in LPRX */
64 #define PPI_D1S_ATMR 0x0148 /* Delay for Data Lane 1 in LPRX */
65 #define PPI_D2S_ATMR 0x014C /* Delay for Data Lane 2 in LPRX */
66 #define PPI_D3S_ATMR 0x0150 /* Delay for Data Lane 3 in LPRX */
68 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* For lane 0 */
69 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* For lane 1 */
70 #define PPI_D2S_CLRSIPOCOUNT 0x016C /* For lane 2 */
71 #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* For lane 3 */
93 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX function */
97 #define DSI_LANEENABLE 0x0210 /* Enables each lane at the Protocol layer. */
98 #define DSI_LANESTATUS0 0x0214 /* Displays lane is in HS RX mode. */
99 #define DSI_LANESTATUS1 0x0218 /* Displays lane is in ULPS or STOP state */
172 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
173 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
176 #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */
273 u8 lvds_link; /* single-link or dual-link */
285 struct device *dev = &tc->dsi->dev; in tc_bridge_pre_enable()
288 ret = regulator_enable(tc->vddio); in tc_bridge_pre_enable()
293 ret = regulator_enable(tc->vdd); in tc_bridge_pre_enable()
298 gpiod_set_value(tc->stby_gpio, 0); in tc_bridge_pre_enable()
301 gpiod_set_value(tc->reset_gpio, 0); in tc_bridge_pre_enable()
308 struct device *dev = &tc->dsi->dev; in tc_bridge_post_disable()
311 gpiod_set_value(tc->reset_gpio, 1); in tc_bridge_post_disable()
314 gpiod_set_value(tc->stby_gpio, 1); in tc_bridge_post_disable()
317 ret = regulator_disable(tc->vdd); in tc_bridge_post_disable()
322 ret = regulator_disable(tc->vddio); in tc_bridge_post_disable()
346 dev_err(&i2c->dev, "Error %d reading from subaddress 0x%x\n", in d2l_read()
360 dev_err(&i2c->dev, "Error %d writing to subaddress 0x%x\n", in d2l_write()
367 struct drm_device *dev = encoder->dev; in get_connector()
370 list_for_each_entry(connector, &dev->mode_config.connector_list, head) in get_connector()
371 if (connector->encoder == encoder) in get_connector()
385 struct drm_connector *connector = get_connector(bridge->encoder); in tc_bridge_enable()
387 mode = &bridge->encoder->crtc->state->adjusted_mode; in tc_bridge_enable()
389 hback_porch = mode->htotal - mode->hsync_end; in tc_bridge_enable()
390 hsync_len = mode->hsync_end - mode->hsync_start; in tc_bridge_enable()
391 vback_porch = mode->vtotal - mode->vsync_end; in tc_bridge_enable()
392 vsync_len = mode->vsync_end - mode->vsync_start; in tc_bridge_enable()
397 hfront_porch = mode->hsync_start - mode->hdisplay; in tc_bridge_enable()
398 hactive = mode->hdisplay; in tc_bridge_enable()
399 vfront_porch = mode->vsync_start - mode->vdisplay; in tc_bridge_enable()
400 vactive = mode->vdisplay; in tc_bridge_enable()
405 d2l_read(tc->i2c, IDREG, &val); in tc_bridge_enable()
407 dev_info(tc->dev, "DSI2LVDS Chip ID.%02x Revision ID. %02x **\n", in tc_bridge_enable()
410 d2l_write(tc->i2c, SYSRST, SYS_RST_REG | SYS_RST_DSIRX | SYS_RST_BM | in tc_bridge_enable()
414 d2l_write(tc->i2c, PPI_TX_RX_TA, TTA_GET | TTA_SURE); in tc_bridge_enable()
415 d2l_write(tc->i2c, PPI_LPTXTIMECNT, LPX_PERIOD); in tc_bridge_enable()
416 d2l_write(tc->i2c, PPI_D0S_CLRSIPOCOUNT, 3); in tc_bridge_enable()
417 d2l_write(tc->i2c, PPI_D1S_CLRSIPOCOUNT, 3); in tc_bridge_enable()
418 d2l_write(tc->i2c, PPI_D2S_CLRSIPOCOUNT, 3); in tc_bridge_enable()
419 d2l_write(tc->i2c, PPI_D3S_CLRSIPOCOUNT, 3); in tc_bridge_enable()
421 val = ((L0EN << tc->num_dsi_lanes) - L0EN) | DSI_CLEN_BIT; in tc_bridge_enable()
422 d2l_write(tc->i2c, PPI_LANEENABLE, val); in tc_bridge_enable()
423 d2l_write(tc->i2c, DSI_LANEENABLE, val); in tc_bridge_enable()
425 d2l_write(tc->i2c, PPI_STARTPPI, PPI_START_FUNCTION); in tc_bridge_enable()
426 d2l_write(tc->i2c, DSI_STARTDSI, DSI_RX_START); in tc_bridge_enable()
428 if (tc->bpc == 8) in tc_bridge_enable()
433 dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000; in tc_bridge_enable()
434 clkdiv = dsiclk / (tc->lvds_link == DUAL_LINK ? DIVIDE_BY_6 : DIVIDE_BY_3); in tc_bridge_enable()
436 t1 = hactive * (tc->bpc * 3 / 8) / tc->num_dsi_lanes; in tc_bridge_enable()
438 t3 = ((t2 * byteclk) / 100) - (hactive * (tc->bpc * 3 / 8) / in tc_bridge_enable()
439 tc->num_dsi_lanes); in tc_bridge_enable()
441 vsdelay = (clkdiv * (t1 + t3) / byteclk) - hback_porch - hsync_len - hactive; in tc_bridge_enable()
444 d2l_write(tc->i2c, VPCTRL, val); in tc_bridge_enable()
446 d2l_write(tc->i2c, HTIM1, htime1); in tc_bridge_enable()
447 d2l_write(tc->i2c, VTIM1, vtime1); in tc_bridge_enable()
448 d2l_write(tc->i2c, HTIM2, htime2); in tc_bridge_enable()
449 d2l_write(tc->i2c, VTIM2, vtime2); in tc_bridge_enable()
451 d2l_write(tc->i2c, VFUEN, VFUEN_EN); in tc_bridge_enable()
452 d2l_write(tc->i2c, SYSRST, SYS_RST_LCD); in tc_bridge_enable()
453 d2l_write(tc->i2c, LVPHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_ND(6)); in tc_bridge_enable()
455 dev_dbg(tc->dev, "bus_formats %04x bpc %d\n", in tc_bridge_enable()
456 connector->display_info.bus_formats[0], in tc_bridge_enable()
457 tc->bpc); in tc_bridge_enable()
460 * with MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA jeida-24 format in tc_bridge_enable()
462 if (connector->display_info.bus_formats[0] == in tc_bridge_enable()
464 /* VESA-24 */ in tc_bridge_enable()
465 d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3)); in tc_bridge_enable()
466 d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0)); in tc_bridge_enable()
467 d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7)); in tc_bridge_enable()
468 d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0)); in tc_bridge_enable()
469 d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2)); in tc_bridge_enable()
470 d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0)); in tc_bridge_enable()
471 d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6)); in tc_bridge_enable()
472 } else { /* MEDIA_BUS_FMT_RGB666_1X7X3_SPWG - JEIDA-18 */ in tc_bridge_enable()
473 d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3)); in tc_bridge_enable()
474 d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_L0, LVI_R5, LVI_G0)); in tc_bridge_enable()
475 d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_L0, LVI_L0)); in tc_bridge_enable()
476 d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0)); in tc_bridge_enable()
477 d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_L0, LVI_L0, LVI_B1, LVI_B2)); in tc_bridge_enable()
478 d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0)); in tc_bridge_enable()
479 d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_L0)); in tc_bridge_enable()
482 d2l_write(tc->i2c, VFUEN, VFUEN_EN); in tc_bridge_enable()
485 if (tc->lvds_link == DUAL_LINK) { in tc_bridge_enable()
491 d2l_write(tc->i2c, LVCFG, val); in tc_bridge_enable()
502 * Maximum pixel clock speed 135MHz for single-link in tc_mode_valid()
503 * 270MHz for dual-link in tc_mode_valid()
505 if ((mode->clock > 135000 && tc->lvds_link == SINGLE_LINK) || in tc_mode_valid()
506 (mode->clock > 270000 && tc->lvds_link == DUAL_LINK)) in tc_mode_valid()
509 switch (info->bus_formats[0]) { in tc_mode_valid()
513 tc->bpc = 8; in tc_mode_valid()
517 tc->bpc = 6; in tc_mode_valid()
520 dev_warn(tc->dev, in tc_mode_valid()
522 info->bus_formats[0]); in tc_mode_valid()
534 int dsi_lanes = -1; in tc358775_parse_dt()
537 * To get the data-lanes of dsi, we need to access the dsi0_out of port1 in tc358775_parse_dt()
540 endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node, in tc358775_parse_dt()
541 TC358775_DSI_IN, -1); in tc358775_parse_dt()
548 dsi_lanes = drm_of_get_data_lanes_count_ep(parent, 1, -1, 1, 4); in tc358775_parse_dt()
556 tc->num_dsi_lanes = dsi_lanes; in tc358775_parse_dt()
558 tc->host_node = of_graph_get_remote_node(np, 0, 0); in tc358775_parse_dt()
559 if (!tc->host_node) in tc358775_parse_dt()
560 return -ENODEV; in tc358775_parse_dt()
562 of_node_put(tc->host_node); in tc358775_parse_dt()
564 tc->lvds_link = SINGLE_LINK; in tc358775_parse_dt()
565 endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node, in tc358775_parse_dt()
566 TC358775_LVDS_OUT1, -1); in tc358775_parse_dt()
573 tc->lvds_link = DUAL_LINK; in tc358775_parse_dt()
578 dev_dbg(tc->dev, "no.of dsi lanes: %d\n", tc->num_dsi_lanes); in tc358775_parse_dt()
579 dev_dbg(tc->dev, "operating in %d-link mode\n", tc->lvds_link); in tc358775_parse_dt()
589 /* Attach the panel-bridge to the dsi bridge */ in tc_bridge_attach()
590 return drm_bridge_attach(bridge->encoder, tc->panel_bridge, in tc_bridge_attach()
591 &tc->bridge, flags); in tc_bridge_attach()
604 struct device *dev = &tc->i2c->dev; in tc_attach_host()
613 host = of_find_mipi_dsi_host_by_node(tc->host_node); in tc_attach_host()
616 return -EPROBE_DEFER; in tc_attach_host()
625 tc->dsi = dsi; in tc_attach_host()
627 dsi->lanes = tc->num_dsi_lanes; in tc_attach_host()
628 dsi->format = MIPI_DSI_FMT_RGB888; in tc_attach_host()
629 dsi->mode_flags = MIPI_DSI_MODE_VIDEO; in tc_attach_host()
642 struct device *dev = &client->dev; in tc_probe()
648 return -ENOMEM; in tc_probe()
650 tc->dev = dev; in tc_probe()
651 tc->i2c = client; in tc_probe()
653 tc->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, in tc_probe()
655 if (IS_ERR(tc->panel_bridge)) in tc_probe()
656 return PTR_ERR(tc->panel_bridge); in tc_probe()
658 ret = tc358775_parse_dt(dev->of_node, tc); in tc_probe()
662 tc->vddio = devm_regulator_get(dev, "vddio-supply"); in tc_probe()
663 if (IS_ERR(tc->vddio)) { in tc_probe()
664 ret = PTR_ERR(tc->vddio); in tc_probe()
665 dev_err(dev, "vddio-supply not found\n"); in tc_probe()
669 tc->vdd = devm_regulator_get(dev, "vdd-supply"); in tc_probe()
670 if (IS_ERR(tc->vdd)) { in tc_probe()
671 ret = PTR_ERR(tc->vdd); in tc_probe()
672 dev_err(dev, "vdd-supply not found\n"); in tc_probe()
676 tc->stby_gpio = devm_gpiod_get(dev, "stby", GPIOD_OUT_HIGH); in tc_probe()
677 if (IS_ERR(tc->stby_gpio)) { in tc_probe()
678 ret = PTR_ERR(tc->stby_gpio); in tc_probe()
679 dev_err(dev, "cannot get stby-gpio %d\n", ret); in tc_probe()
683 tc->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); in tc_probe()
684 if (IS_ERR(tc->reset_gpio)) { in tc_probe()
685 ret = PTR_ERR(tc->reset_gpio); in tc_probe()
686 dev_err(dev, "cannot get reset-gpios %d\n", ret); in tc_probe()
690 tc->bridge.funcs = &tc_bridge_funcs; in tc_probe()
691 tc->bridge.of_node = dev->of_node; in tc_probe()
692 drm_bridge_add(&tc->bridge); in tc_probe()
703 drm_bridge_remove(&tc->bridge); in tc_probe()
711 drm_bridge_remove(&tc->bridge); in tc_remove()