| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_hwseq.c | 43 hws->ctx
45 hws->regs->reg
49 hws->shifts->field_name, hws->masks->field_name
63 …config->gart_config.page_table_base_addr = ((uint64_t)page_table_base_hi << 32) | page_table_base_… in mmhub_update_page_table_config()
67 int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_co… in dcn21_init_sys_ctx() argument
71 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; in dcn21_init_sys_ctx()
72 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; in dcn21_init_sys_ctx()
73 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; in dcn21_init_sys_ctx()
74 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; in dcn21_init_sys_ctx()
75 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; in dcn21_init_sys_ctx()
[all …]
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_hwseq.c | 62 hws->ctx
64 hws->regs->reg
66 dc->ctx->logger
71 hws->shifts->field_name, hws->masks->field_name
76 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut()
80 if (plane_state->blend_tf) { in dcn30_set_blend_lut()
81 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) in dcn30_set_blend_lut()
82 blend_lut = &plane_state->blend_tf->pwl; in dcn30_set_blend_lut()
83 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { in dcn30_set_blend_lut()
85 plane_state->blend_tf, &dpp_base->regamma_params, false); in dcn30_set_blend_lut()
[all …]
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hwseq.c | 63 hws->ctx
65 hws->regs->reg
69 hws->shifts->field_name, hws->masks->field_name
71 static int find_free_gsl_group(const struct dc *dc) in find_free_gsl_group() argument
73 if (dc->res_pool->gsl_groups.gsl_0 == 0) in find_free_gsl_group()
75 if (dc->res_pool->gsl_groups.gsl_1 == 0) in find_free_gsl_group()
77 if (dc->res_pool->gsl_groups.gsl_2 == 0) in find_free_gsl_group()
89 * - immediate flip: find first available GSL group if not already assigned
92 * - vsync flip: disable GSL if used
95 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_hwseq.c | 58 hws->ctx
60 hws->regs->reg
62 dc->ctx->logger
67 hws->shifts->field_name, hws->masks->field_name
69 static void enable_memory_low_power(struct dc *dc) in enable_memory_low_power() argument
71 struct dce_hwseq *hws = dc->hwseq; in enable_memory_low_power()
74 if (dc->debug.enable_mem_low_power.bits.dmcu) { in enable_memory_low_power()
76 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { in enable_memory_low_power()
82 if (dc->debug.enable_mem_low_power.bits.optc) { in enable_memory_low_power()
87 if (dc->debug.enable_mem_low_power.bits.vga) { in enable_memory_low_power()
[all …]
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| /Linux-v6.1/drivers/tty/ |
| D | nozomi.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * nozomi.c -- HSDPA driver Broadband Wireless Data Card - Globe Trotter
18 * --------------------------------------------------------------------------
25 * --------------------------------------------------------------------------
78 if (tbuf[data_len - 2] == '\r') \
79 tbuf[data_len - 2] = 'r'; \
148 F32_2 = 2048, /* 512 bytes downlink + uplink * 2 -> 2048 */
149 F32_8 = 8192, /* 3072 bytes downl. + 1024 bytes uplink * 2 -> 8192 */
173 CTRL_ERROR = -1,
183 PORT_ERROR = -1,
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| /Linux-v6.1/drivers/gpu/drm/bridge/imx/ |
| D | imx8qxp-pixel-link.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/media-bus-format.h>
18 #include <dt-bindings/firmware/imx/rsrc.h>
20 #define DRIVER_NAME "imx8qxp-display-pixel-link"
43 ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc, in imx8qxp_pixel_link_enable_mst_en()
44 pl->mst_en_ctrl, true); in imx8qxp_pixel_link_enable_mst_en()
46 DRM_DEV_ERROR(pl->dev, in imx8qxp_pixel_link_enable_mst_en()
47 "failed to enable DC%u stream%u pixel link mst_en: %d\n", in imx8qxp_pixel_link_enable_mst_en()
48 pl->dc_id, pl->stream_id, ret); in imx8qxp_pixel_link_enable_mst_en()
55 ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc, in imx8qxp_pixel_link_enable_mst_vld()
[all …]
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| /Linux-v6.1/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_psr.c | 27 #include "dc.h"
34 struct dc *dc = link->ctx->dc; in link_supports_psrsu() local
36 if (!dc->caps.dmcub_support) in link_supports_psrsu()
39 if (dc->ctx->dce_version < DCN_VERSION_3_1) in link_supports_psrsu()
45 if (!link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP || in link_supports_psrsu()
46 !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED) in link_supports_psrsu()
49 if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED && in link_supports_psrsu()
50 !link->dpcd_caps.psr_info.psr2_su_y_granularity_cap) in link_supports_psrsu()
57 * amdgpu_dm_set_psr_caps() - set link psr capabilities
63 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) { in amdgpu_dm_set_psr_caps()
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| D | amdgpu_dm_crc.c | 31 #include "dc.h"
88 struct drm_device *drm_dev = crtc->dev; in amdgpu_dm_set_crc_window_default()
91 spin_lock_irq(&drm_dev->event_lock); in amdgpu_dm_set_crc_window_default()
92 acrtc->dm_irq_params.crc_window.x_start = 0; in amdgpu_dm_set_crc_window_default()
93 acrtc->dm_irq_params.crc_window.y_start = 0; in amdgpu_dm_set_crc_window_default()
94 acrtc->dm_irq_params.crc_window.x_end = 0; in amdgpu_dm_set_crc_window_default()
95 acrtc->dm_irq_params.crc_window.y_end = 0; in amdgpu_dm_set_crc_window_default()
96 acrtc->dm_irq_params.crc_window.activated = false; in amdgpu_dm_set_crc_window_default()
97 acrtc->dm_irq_params.crc_window.update_win = false; in amdgpu_dm_set_crc_window_default()
98 acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; in amdgpu_dm_set_crc_window_default()
[all …]
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| D | amdgpu_dm_crtc.c | 1 // SPDX-License-Identifier: MIT
29 #include "dc.h"
39 struct drm_crtc *crtc = &acrtc->base; in dm_crtc_handle_vblank()
40 struct drm_device *dev = crtc->dev; in dm_crtc_handle_vblank()
45 spin_lock_irqsave(&dev->event_lock, flags); in dm_crtc_handle_vblank()
47 /* Send completion event for cursor-only commits */ in dm_crtc_handle_vblank()
48 if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { in dm_crtc_handle_vblank()
49 drm_crtc_send_vblank_event(crtc, acrtc->event); in dm_crtc_handle_vblank()
51 acrtc->event = NULL; in dm_crtc_handle_vblank()
54 spin_unlock_irqrestore(&dev->event_lock, flags); in dm_crtc_handle_vblank()
[all …]
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| D | amdgpu_dm_hdcp.c | 45 struct i2c_command cmd = {i2c_payloads, 1, I2C_COMMAND_ENGINE_HW, link->dc->caps.i2c_speed_in_khz}; in lp_write_i2c()
47 return dm_helpers_submit_i2c(link->ctx, link, &cmd); in lp_write_i2c()
56 struct i2c_command cmd = {i2c_payloads, 2, I2C_COMMAND_ENGINE_HW, link->dc->caps.i2c_speed_in_khz}; in lp_read_i2c()
58 return dm_helpers_submit_i2c(link->ctx, link, &cmd); in lp_read_i2c()
66 return dm_helpers_dp_write_dpcd(link->ctx, link, address, data, size); in lp_write_dpcd()
74 return dm_helpers_dp_read_dpcd(link->ctx, link, address, data, size); in lp_read_dpcd()
82 if (!psp->hdcp_context.context.initialized) { in psp_get_srm()
87 hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf; in psp_get_srm()
90 hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP_GET_SRM; in psp_get_srm()
91 psp_hdcp_invoke(psp, hdcp_cmd->cmd_id); in psp_get_srm()
[all …]
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| D | amdgpu_dm_irq.c | 27 #include "dc.h"
46 * What DM provides on top are two IRQ tables specifically for top-half and
47 * bottom-half IRQ handling, with the bottom-half implementing workqueues:
49 * - &amdgpu_display_manager.irq_handler_list_high_tab
50 * - &amdgpu_display_manager.irq_handler_list_low_tab
59 * To expose DC's hardware interrupt toggle to the base driver, DM implements
61 * amdgpu_irq_update() to enable or disable the interrupt.
69 * struct amdgpu_dm_irq_handler_data - Data for DM interrupt handlers.
75 * @irq_source: DC interrupt source that this handler is registered for
90 spin_lock_irqsave(&adev->dm.irq_handler_list_table_lock, flags)
[all …]
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn314/ |
| D | dcn314_hwseq.c | 1 // SPDX-License-Identifier: MIT
63 hws->ctx
65 hws->regs->reg
67 dc->ctx->logger
72 hws->shifts->field_name, hws->masks->field_name
77 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); in calc_mpc_flow_ctrl_cnt()
83 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - in calc_mpc_flow_ctrl_cnt()
84 stream->timing.h_border_left - in calc_mpc_flow_ctrl_cnt()
85 stream->timing.h_border_right; in calc_mpc_flow_ctrl_cnt()
99 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream()
[all …]
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer.c | 65 hws->ctx
67 hws->regs->reg
71 hws->shifts->field_name, hws->masks->field_name
86 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
95 void dcn10_lock_all_pipes(struct dc *dc, in dcn10_lock_all_pipes() argument
103 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
104 pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes()
105 tg = pipe_ctx->stream_res.tg; in dcn10_lock_all_pipes()
111 if (pipe_ctx->top_pipe || in dcn10_lock_all_pipes()
112 !pipe_ctx->stream || in dcn10_lock_all_pipes()
[all …]
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| /Linux-v6.1/drivers/power/supply/ |
| D | max8903_charger.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * max8903_charger.c - Maxim 8903 USB/Adapter Charger Driver
29 struct gpio_desc *dok; /* DC (Adapter) Power OK output */
33 struct gpio_desc *dcm; /* Current-Limit Mode input (1: DC, 2: USB) */
54 val->intval = POWER_SUPPLY_STATUS_UNKNOWN; in max8903_get_property()
55 if (data->chg) { in max8903_get_property()
56 if (gpiod_get_value(data->chg)) in max8903_get_property()
58 val->intval = POWER_SUPPLY_STATUS_CHARGING; in max8903_get_property()
59 else if (data->usb_in || data->ta_in) in max8903_get_property()
60 val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; in max8903_get_property()
[all …]
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_stream.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
28 #include "dc.h"
35 #define DC_LOGGER dc->ctx->logger
42 if (sink->sink_signal == SIGNAL_TYPE_NONE) in update_stream_signal()
43 stream->signal = stream->link->connector_signal; in update_stream_signal()
45 stream->signal = sink->sink_signal; in update_stream_signal()
47 if (dc_is_dvi_signal(stream->signal)) { in update_stream_signal()
48 if (stream->ctx->dc->caps.dual_link_dvi && in update_stream_signal()
49 (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK && in update_stream_signal()
50 sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) in update_stream_signal()
[all …]
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_optc.c | 31 #include "dc.h"
36 optc1->tg_regs->reg
39 optc1->base.ctx
43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
50 int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right; in optc32_set_odm_combine()
97 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc32_set_odm_combine()
98 optc1->opp_count = opp_cnt; in optc32_set_odm_combine()
110 * Enable CRTC - call ASIC Control Object to enable Timing generator.
118 OPTC_SEG0_SRC_SEL, optc->inst); in optc32_enable_crtc()
142 /* disable otg request until end of the first line in optc32_disable_crtc()
[all …]
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| D | dcn32_hwseq.c | 59 hws->ctx
61 hws->regs->reg
63 dc->ctx->logger
68 hws->shifts->field_name, hws->masks->field_name
79 if (hws->ctx->dc->debug.disable_dsc_power_gate) in dcn32_dsc_pg_control()
133 bool force_on = true; /* disable power gating */ in dcn32_enable_power_gating_plane()
156 if (hws->ctx->dc->debug.disable_hubp_power_gate) in dcn32_hubp_pg_control()
185 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) in dcn32_check_no_memory_request_for_cab() argument
189 /* First, check no-memory-request case */ in dcn32_check_no_memory_request_for_cab()
190 for (i = 0; i < dc->current_state->stream_count; i++) { in dcn32_check_no_memory_request_for_cab()
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/power/supply/ |
| D | qcom,pm8941-charger.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/supply/qcom,pm8941-charger.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Switch-Mode Battery Charger and Boost
10 - Sebastian Reichel <sre@kernel.org>
15 - qcom,pm8226-charger
16 - qcom,pm8941-charger
23 - description: charge done
24 - description: charge fast mode
[all …]
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| /Linux-v6.1/arch/sparc/include/asm/ |
| D | fhc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
42 #define FHC_CONTROL_LFAT 0x00040000 /* AC/DC signalled a local error */
44 #define FHC_CONTROL_DCD 0x00008000 /* DC-->DC Converter Disable */
45 #define FHC_CONTROL_POFF 0x00004000 /* AC/DC Controller PLL Disable */
46 #define FHC_CONTROL_FOFF 0x00002000 /* FHC Controller PLL Disable */
|
| /Linux-v6.1/Documentation/devicetree/bindings/iio/dac/ |
| D | adi,ad5755.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD5755 Multi-Channel DAC
10 - Sean Nyekjaer <sean.nyekjaer@prevas.dk>
15 - adi,ad5755
16 - adi,ad5755-1
17 - adi,ad5757
18 - adi,ad5735
19 - adi,ad5737
[all …]
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| /Linux-v6.1/drivers/pwm/ |
| D | pwm-bcm-kona.c | 1 // SPDX-License-Identifier: GPL-2.0-only
20 * 1) There is no disable bit and the hardware docs advise programming a zero
21 * duty to achieve output equivalent to that of a normal disable operation.
75 unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET); in kona_pwmc_prepare_for_settings()
79 writel(value, kp->base + PWM_CONTROL_OFFSET); in kona_pwmc_prepare_for_settings()
90 unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET); in kona_pwmc_apply_settings()
95 writel(value, kp->base + PWM_CONTROL_OFFSET); in kona_pwmc_apply_settings()
106 unsigned long prescale = PRESCALE_MIN, pc, dc; in kona_pwmc_config() local
107 unsigned int value, chan = pwm->hwpwm; in kona_pwmc_config()
114 * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE in kona_pwmc_config()
[all …]
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_hw_sequencer.c | 27 #include "dc.h"
75 * For eDP, after power-up/power/down,
85 hws->ctx
90 hws->regs->reg
94 hws->shifts->field_name, hws->masks->field_name
102 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
105 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
108 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
111 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
204 struct dc *dc, in dce110_enable_display_power_gating() argument
[all …]
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/link/ |
| D | link_hwss_hpo_dp.c | 34 switch (link->link_enc->transmitter) { in get_phyd32clk_src()
54 pipe_ctx->stream_res.hpo_dp_stream_enc; in set_hpo_dp_throttled_vcp_size()
56 pipe_ctx->link_res.hpo_dp_link_enc; in set_hpo_dp_throttled_vcp_size()
58 hpo_dp_link_encoder->funcs->set_throttled_vcp_size(hpo_dp_link_encoder, in set_hpo_dp_throttled_vcp_size()
59 hpo_dp_stream_encoder->inst, in set_hpo_dp_throttled_vcp_size()
68 pipe_ctx->stream_res.hpo_dp_stream_enc; in set_hpo_dp_hblank_min_symbol_width()
69 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; in set_hpo_dp_hblank_min_symbol_width()
72 dc_link_bandwidth_kbps(pipe_ctx->stream->link, link_settings); in set_hpo_dp_hblank_min_symbol_width()
77 timing->h_total - timing->h_addressable), in set_hpo_dp_hblank_min_symbol_width()
78 dc_fixpt_from_fraction(timing->pix_clk_100hz, 10)); in set_hpo_dp_hblank_min_symbol_width()
[all …]
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| /Linux-v6.1/drivers/gpu/drm/tegra/ |
| D | hub.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
26 #include "dc.h"
65 * be filtered out later on by ->format_mod_supported() on SoCs where
82 offset = 0x000 + (offset - 0x500); in tegra_plane_offset()
83 return plane->offset + offset; in tegra_plane_offset()
87 offset = 0x180 + (offset - 0x700); in tegra_plane_offset()
88 return plane->offset + offset; in tegra_plane_offset()
92 offset = 0x1c0 + (offset - 0x800); in tegra_plane_offset()
93 return plane->offset + offset; in tegra_plane_offset()
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| D | rgb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 #include "dc.h"
18 struct tegra_dc *dc; member
80 static void tegra_dc_write_regs(struct tegra_dc *dc, in tegra_dc_write_regs() argument
87 tegra_dc_writel(dc, table[i].value, table[i].offset); in tegra_dc_write_regs()
95 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable)); in tegra_rgb_encoder_disable()
96 tegra_dc_commit(rgb->dc); in tegra_rgb_encoder_disable()
105 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable)); in tegra_rgb_encoder_enable()
108 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); in tegra_rgb_encoder_enable()
111 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1)); in tegra_rgb_encoder_enable()
[all …]
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