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/Linux-v5.15/include/linux/
Dclk-provider.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
31 /* parents need enable during gate/ungate, set rate and re-parent */
42 * struct clk_rate_request - Structure encoding the clk constraints that
64 * struct clk_duty - Struture encoding the duty cycle ratio of a clock
75 * struct clk_ops - Callback operations for hardware clocks; these are to
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/Linux-v5.15/Documentation/devicetree/bindings/net/
Dgpmc-eth.txt1 Device tree bindings for Ethernet chip connected to TI GPMC
4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
15 refer to the binding documentation of the device. For example, the documentation
18 Child nodes need to specify the GPMC bus address width using the "bank-width"
20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21 address width, it supports devices with 32-bit word registers.
23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit
27 and 16-bit devices and so must be either 1 or 2 bytes.
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/Linux-v5.15/drivers/media/platform/sti/hva/
Dhva-v4l2.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <media/v4l2-event.h>
13 #include <media/v4l2-ioctl.h>
14 #include <media/videobuf2-dma-contig.h>
17 #include "hva-hw.h"
86 * of a stream is estimated to ((width x height x 3 / 2) / 2) in estimated_stream_size()
93 struct hva_frameinfo *frameinfo = &ctx->frameinfo; in set_default_params()
94 struct hva_streaminfo *streaminfo = &ctx->streaminfo; in set_default_params()
96 frameinfo->pixelformat = V4L2_PIX_FMT_NV12; in set_default_params()
97 frameinfo->width = HVA_DEFAULT_WIDTH; in set_default_params()
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/Linux-v5.15/drivers/media/platform/exynos4-is/
Dfimc-core.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
21 #include <media/media-entity.h>
22 #include <media/videobuf2-v4l2.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-mem2mem.h>
26 #include <media/v4l2-mediabus.h>
27 #include <media/drv-intf/exynos-fimc.h>
35 #define FIMC_DRIVER_NAME "exynos4-fimc"
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/Linux-v5.15/Documentation/devicetree/bindings/mtd/
Dmtd-physmap.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
10 - Rob Herring <robh@kernel.org>
19 - items:
20 - enum:
21 - amd,s29gl01gp
22 - amd,s29gl032a
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/Linux-v5.15/drivers/clk/
Dclk-divider.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
10 #include <linux/clk-provider.h>
11 #include <linux/device.h>
23 * prepare - clk_prepare only ensures that parents are prepared
24 * enable - clk_enable only ensures that parents are enabled
25 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
26 * parent - fixed parent. No clk_set_parent support
31 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_readl()
32 return ioread32be(divider->reg); in clk_div_readl()
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/Linux-v5.15/drivers/dma/
Dfsldma.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
12 #include <linux/device.h>
108 u32 mr; /* 0x00 - Mode Register */
109 u32 sr; /* 0x04 - Status Register */
110 u64 cdar; /* 0x08 - Current descriptor address register */
111 u64 sar; /* 0x10 - Source Address Register */
112 u64 dar; /* 0x18 - Destination Address Register */
113 u32 bcr; /* 0x20 - Byte Count Register */
114 u64 ndar; /* 0x24 - Next Descriptor Address Register */
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/Linux-v5.15/drivers/media/usb/stk1160/
Dstk1160-v4l.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * <elezegarcia--a.t--gmail.com>
10 * <rmthomas--a.t--sciolus.org>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-common.h>
21 #include <media/v4l2-ioctl.h>
22 #include <media/v4l2-fh.h>
23 #include <media/v4l2-event.h>
24 #include <media/videobuf2-vmalloc.h>
29 #include "stk1160-reg.h"
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/Linux-v5.15/Documentation/devicetree/bindings/memory-controllers/
Dti-aemif.txt1 * Device tree bindings for Texas instruments AEMIF controller
4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
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/Linux-v5.15/drivers/gpio/
Dgpio-xilinx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2008 - 2013 Xilinx, Inc.
45 * struct xgpio_instance - Stores information about GPIO device
54 * @irq: IRQ used by GPIO device
80 return bitmap_bitremap(bit, chip->hw_map, chip->sw_map, 64); in xgpio_from_bit()
85 return bitmap_bitremap(gpio, chip->sw_map, chip->hw_map, 64); in xgpio_to_bit()
113 return -EINVAL; in xgpio_regoffset()
119 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); in xgpio_read_ch()
125 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); in xgpio_write_ch()
131 int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1); in xgpio_read_ch_all()
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/Linux-v5.15/drivers/clk/imx/
Dclk.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/clk-provider.h>
88 #define imx_clk_divider(name, parent, reg, shift, width) \ argument
89 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
91 #define imx_clk_divider2(name, parent, reg, shift, width) \ argument
92 to_clk(imx_clk_hw_divider2(name, parent, reg, shift, width))
94 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \ argument
95 to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
118 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \ argument
119 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
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/Linux-v5.15/samples/vfio-mdev/
Dmdpy-fb.c1 // SPDX-License-Identifier: GPL-2.0
3 * Framebuffer driver for mdpy (mediated virtual pci display device).
5 * See mdpy-defs.h for device specs
26 #include "mdpy-defs.h"
29 .id = "mdpy-fb",
36 .height = -1,
37 .width = -1,
61 u32 *pal = info->pseudo_palette; in mdpy_fb_setcolreg()
62 u32 cr = red >> (16 - info->var.red.length); in mdpy_fb_setcolreg()
63 u32 cg = green >> (16 - info->var.green.length); in mdpy_fb_setcolreg()
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/Linux-v5.15/Documentation/userspace-api/media/v4l/
Dcrop.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
6 Image Cropping, Insertion and Scaling -- the CROP API
12 <selection-api>`. The new API should be preferred in most cases,
15 equivalent in the SELECTION API. See :ref:`selection-vs-crop` for a
34 device the source is the video signal, and the cropping ioctls determine
40 On a video output device the source are the images passed in by the
47 Source and target rectangles are defined even if the device does not
62 .. _crop-scale:
64 .. kernel-figure:: crop.svg
74 For capture devices the coordinates of the top left corner, width and
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Dvidioc-enum-framesizes.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_ENUM_FRAMESIZES - Enumerate frame sizes
30 that contains an index and pixel format and receives a frame width
36 This ioctl allows applications to enumerate all frame sizes (i. e. width
37 and height in pixels) that the device supports for the given pixel
44 depend on the type of frame sizes the device supports. Here are the
47 - **Discrete:** The function returns success if the given index value
48 (zero-based) is valid. The application should increase the index by
54 - **Step-wise:** The function returns success if the given index value
60 - **Continuous:** This is a special case of the step-wise type above.
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/Linux-v5.15/drivers/accessibility/braille/
Dbraille_console.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Minimalistic braille device kernel support.
5 * By default, shows console messages on the braille device.
8 * Copyright (C) Samuel Thibault <samuel.thibault@ens-lyon.org>
25 MODULE_AUTHOR("samuel.thibault@ens-lyon.org");
26 MODULE_DESCRIPTION("braille device");
30 * Braille device support part.
45 #define WIDTH 40 macro
47 static u16 console_buf[WIDTH];
57 static int lastVC = -1;
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/Linux-v5.15/include/media/
Dv4l2-common.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 internal low-level v4l2 drivers.
18 #include <media/v4l2-dev.h>
20 /* Common printk constructs for v4l-i2c drivers. These macros create a unique
24 printk(level "%s %d-%04x: " fmt, name, i2c_adapter_id(adapter), addr , ## arg)
27 v4l_printk(level, (client)->dev.driver->name, (client)->adapter, \
28 (client)->addr, fmt , ## arg)
54 /* ------------------------------------------------------------------------- */
58 printk(level "%s: " fmt, (dev)->name , ## arg)
78 * v4l2_ctrl_query_fill- Fill in a struct v4l2_queryctrl
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/Linux-v5.15/Documentation/devicetree/bindings/misc/
Dxlnx,sd-fec.txt4 which provides high-throughput LDPC and Turbo Code implementations.
6 customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
12 - compatible: Must be "xlnx,sd-fec-1.1"
13 - clock-names : List of input clock names from the following:
14 - "core_clk", Main processing clock for processing core (required)
15 - "s_axi_aclk", AXI4-Lite memory-mapped slave interface clock (required)
16 - "s_axis_din_aclk", DIN AXI4-Stream Slave interface clock (optional)
17 - "s_axis_din_words-aclk", DIN_WORDS AXI4-Stream Slave interface clock (optional)
18 - "s_axis_ctrl_aclk", Control input AXI4-Stream Slave interface clock (optional)
19 - "m_axis_dout_aclk", DOUT AXI4-Stream Master interface clock (optional)
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/Linux-v5.15/drivers/media/platform/qcom/camss/
Dcamss-vfe.c1 // SPDX-License-Identifier: GPL-2.0
3 * camss-vfe.c
5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module
7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 * Copyright (C) 2015-2018 Linaro Ltd.
20 #include <media/media-entity.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-subdev.h>
24 #include "camss-vfe.h"
126 * vfe_get_bpp - map media bus format to bits per pixel
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/Linux-v5.15/drivers/media/platform/omap3isp/
Dispresizer.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - Resizer module
14 #include <linux/device.h>
42 * "TRM ES3.1, table 12-46"
59 * 7-tap mode is for scale factors 0.25x to 0.5x.
60 * 4-tap mode is for scale factors 0.5x to 4.0x.
64 /* For 8-phase 4-tap horizontal filter: */
75 /* For 8-phase 4-tap vertical filter: */
86 /* For 4-phase 7-tap horizontal filter: */
94 /* For 4-phase 7-tap vertical filter: */
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/Linux-v5.15/drivers/mtd/maps/
Dpismo.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PISMO memory driver - http://www.pismoworld.org/
15 #include <linux/mtd/plat-ram.h>
22 u8 width; member
26 char device[32]; member
39 u8 width; member
52 struct i2c_client *client = to_i2c_client(pdev->dev.parent); in pismo_set_vpp()
55 pismo->vpp(pismo->vpp_data, on); in pismo_set_vpp()
58 static unsigned int pismo_width_to_bytes(unsigned int width) in pismo_width_to_bytes() argument
60 width &= 15; in pismo_width_to_bytes()
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/Linux-v5.15/drivers/video/fbdev/
Dtgafb.c2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
18 #include <linux/device.h>
36 #define TGA_BUS_TC(dev) (dev->bus == &tc_bus_type)
58 static int tgafb_register(struct device *dev);
59 static void tgafb_unregister(struct device *dev);
109 return tgafb_register(&pdev->dev); in tgafb_pci_register()
114 tgafb_unregister(&pdev->dev); in tgafb_pci_unregister()
122 static int tgafb_tc_register(struct device *);
123 static int tgafb_tc_unregister(struct device *);
126 { "DEC ", "PMAGD-AA" },
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/Linux-v5.15/drivers/media/platform/xilinx/
Dxilinx-vip.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2015 Ideas on Board
6 * Copyright (C) 2013-2015 Xilinx, Inc.
18 #include <dt-bindings/media/xilinx-vip.h>
20 #include "xilinx-vip.h"
22 /* -----------------------------------------------------------------------------
46 * xvip_get_format_by_code - Retrieve format information for a media bus code
60 if (format->code == code) in xvip_get_format_by_code()
64 return ERR_PTR(-EINVAL); in xvip_get_format_by_code()
69 * xvip_get_format_by_fourcc - Retrieve format information for a 4CC
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/Linux-v5.15/drivers/staging/media/imx/
Dimx8mq-mipi-csi2.c1 // SPDX-License-Identifier: GPL-2.0
3 * NXP i.MX8MQ SoC series MIPI-CSI2 receiver driver
9 #include <linux/clk-provider.h>
28 #include <media/v4l2-common.h>
29 #include <media/v4l2-device.h>
30 #include <media/v4l2-fwnode.h>
31 #include <media/v4l2-mc.h>
32 #include <media/v4l2-subdev.h>
34 #define MIPI_CSI2_DRIVER_NAME "imx8mq-mipi-csi2"
46 /* i.MX8MQ CSI-2 controller CSR */
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/Linux-v5.15/drivers/media/platform/sti/delta/
Ddelta.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <media/v4l2-device.h>
12 #include <media/v4l2-mem2mem.h>
14 #include "delta-cfg.h"
17 * enum delta_state - state of decoding instance
46 * struct delta_streaminfo - information about stream to decode
49 * @width: width of video stream
69 u32 width; member
89 * struct delta_au - access unit structure.
112 * struct delta_frameinfo - information about decoded frame
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/Linux-v5.15/drivers/media/platform/sunxi/sun8i-di/
Dsun8i-di.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-ioctl.h>
22 #include <media/v4l2-mem2mem.h>
24 #include "sun8i-di.h"
35 return readl(dev->base + reg); in deinterlace_read()
41 writel(value, dev->base + reg); in deinterlace_write()
47 writel(readl(dev->base + reg) | bits, dev->base + reg); in deinterlace_set_bits()
53 u32 val = readl(dev->base + reg); in deinterlace_clr_set_bits()
58 writel(val, dev->base + reg); in deinterlace_clr_set_bits()
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