1 /* SPDX-License-Identifier: GPL-2.0 */
3  *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4  *  Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14  * top-level framework.  custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
31 /* parents need enable during gate/ungate, set rate and re-parent */
42  * struct clk_rate_request - Structure encoding the clk constraints that
64  * struct clk_duty - Struture encoding the duty cycle ratio of a clock
75  * struct clk_ops -  Callback operations for hardware clocks; these are to
122  *		Returns the calculated rate.  Optional, but recommended - if
138  *		Returns 0 on success, -EERROR otherwise.
154  *		Returns 0 on success, -EERROR otherwise.
165  *		Returns 0 on success, -EERROR otherwise.
170  *		Returns the calculated accuracy.  Optional - if	this op is not
175  *		Returned values are 0-359 degrees on success, negative
180  *		0-359. Return 0 on success, otherwise -EERROR.
189  *              and >= numerator) Return 0 on success, otherwise -EERROR.
191  * @init:	Perform platform-specific initialization magic.
198  *		Returns 0 on success, -EERROR otherwise.
202  * @debug_init:	Set up type-specific debugfs entries for this clock.  This
206  *		prepare_lock held.  Returns 0 on success, -EERROR otherwise.
216  * (eg. when a device is opened), and clk_enable when the clock is actually
258  * struct clk_parent_data - clk parent information
272  * struct clk_init_data - holds init data that's common to all clocks and is
283  * @flags: framework-level hints and quirks
297  * struct clk_hw - handle for traversing from a struct clk to its corresponding
298  * hardware-specific structure.  struct clk_hw should be declared within struct
305  * @clk: pointer to the per-user struct clk instance that can be used to call
328  * struct clk_fixed_rate - fixed-rate clock
329  * @hw:		handle between common and hardware-specific interfaces
335  * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
348 struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
354 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
358  * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
360  * @dev: device that is registering this clock
363  * @flags: framework-specific flags
364  * @fixed_rate: non-adjustable clock rate
370  * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
372  * @dev: device that is registering this clock
375  * @flags: framework-specific flags
376  * @fixed_rate: non-adjustable clock rate
383  * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
385  * @dev: device that is registering this clock
388  * @flags: framework-specific flags
389  * @fixed_rate: non-adjustable clock rate
397  * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
399  * @dev: device that is registering this clock
402  * @flags: framework-specific flags
403  * @fixed_rate: non-adjustable clock rate
404  * @fixed_accuracy: non-adjustable clock accuracy
413  * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
415  * @dev: device that is registering this clock
418  * @flags: framework-specific flags
419  * @fixed_rate: non-adjustable clock rate
420  * @fixed_accuracy: non-adjustable clock accuracy
428  * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
430  * @dev: device that is registering this clock
433  * @flags: framework-specific flags
434  * @fixed_rate: non-adjustable clock rate
435  * @fixed_accuracy: non-adjustable clock accuracy
449  * struct clk_gate - gating clock
451  * @hw:		handle between common and hardware-specific interfaces
454  * @flags:	hardware-specific flags
460  * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
463  * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
464  *	of this register, and mask of gate bits are in higher 16-bit of this
465  *	register.  While setting the gate bits, higher 16-bit should also be
467  * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
486 struct clk_hw *__clk_hw_register_gate(struct device *dev,
493 struct clk *clk_register_gate(struct device *dev, const char *name,
498  * clk_hw_register_gate - register a gate clock with the clock framework
499  * @dev: device that is registering this clock
502  * @flags: framework-specific flags for this clock
505  * @clk_gate_flags: gate-specific flags for this clock
514  * clk_hw_register_gate_parent_hw - register a gate clock with the clock
516  * @dev: device that is registering this clock
519  * @flags: framework-specific flags for this clock
522  * @clk_gate_flags: gate-specific flags for this clock
531  * clk_hw_register_gate_parent_data - register a gate clock with the clock
533  * @dev: device that is registering this clock
536  * @flags: framework-specific flags for this clock
539  * @clk_gate_flags: gate-specific flags for this clock
557  * struct clk_divider - adjustable divider clock
559  * @hw:		handle between common and hardware-specific interfaces
562  * @width:	width of the divider bit field
570  * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
574  * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
576  * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors.  For dividers which have
581  * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
582  *	of this register, and mask of divider bits are in higher 16-bit of this
583  *	register.  While setting the divider bits, higher 16-bit should also be
585  * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
587  * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
589  * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
591  *	2^width of the field.
592  * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
600 	u8		width;  member
606 #define clk_div_mask(width)	((1 << (width)) - 1)  argument
623 		unsigned long flags, unsigned long width);
627 			       u8 width, unsigned long flags);
630 				  const struct clk_div_table *table, u8 width,
633 			   const struct clk_div_table *table, u8 width,
636 			      const struct clk_div_table *table, u8 width,
639 		const struct clk_div_table *table, u8 width,
642 struct clk_hw *__clk_hw_register_divider(struct device *dev,
646 		void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
648 struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
652 		void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
654 struct clk *clk_register_divider_table(struct device *dev, const char *name,
656 		void __iomem *reg, u8 shift, u8 width,
660  * clk_register_divider - register a divider clock with the clock framework
661  * @dev: device registering this clock
664  * @flags: framework-specific flags
667  * @width: width of the bitfield
668  * @clk_divider_flags: divider-specific flags for this clock
671 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \  argument
674 				   (reg), (shift), (width),		       \
677  * clk_hw_register_divider - register a divider clock with the clock framework
678  * @dev: device registering this clock
681  * @flags: framework-specific flags
684  * @width: width of the bitfield
685  * @clk_divider_flags: divider-specific flags for this clock
689 				width, clk_divider_flags, lock)		      \  argument
691 				  NULL, (flags), (reg), (shift), (width),     \
694  * clk_hw_register_divider_parent_hw - register a divider clock with the clock
696  * @dev: device registering this clock
699  * @flags: framework-specific flags
702  * @width: width of the bitfield
703  * @clk_divider_flags: divider-specific flags for this clock
707 					  shift, width, clk_divider_flags,    \  argument
710 				  NULL, (flags), (reg), (shift), (width),     \
713  * clk_hw_register_divider_parent_data - register a divider clock with the clock
715  * @dev: device registering this clock
718  * @flags: framework-specific flags
721  * @width: width of the bitfield
722  * @clk_divider_flags: divider-specific flags for this clock
726 					    reg, shift, width,		      \  argument
730 				  (width), (clk_divider_flags), NULL, (lock))
732  * clk_hw_register_divider_table - register a table based divider clock with
734  * @dev: device registering this clock
737  * @flags: framework-specific flags
740  * @width: width of the bitfield
741  * @clk_divider_flags: divider-specific flags for this clock
746 				      shift, width, clk_divider_flags, table, \  argument
749 				  NULL, (flags), (reg), (shift), (width),     \
752  * clk_hw_register_divider_table_parent_hw - register a table based divider
754  * @dev: device registering this clock
757  * @flags: framework-specific flags
760  * @width: width of the bitfield
761  * @clk_divider_flags: divider-specific flags for this clock
766 						reg, shift, width,	      \  argument
770 				  NULL, (flags), (reg), (shift), (width),     \
773  * clk_hw_register_divider_table_parent_data - register a table based divider
775  * @dev: device registering this clock
778  * @flags: framework-specific flags
781  * @width: width of the bitfield
782  * @clk_divider_flags: divider-specific flags for this clock
787 						  flags, reg, shift, width,   \  argument
792 				  (width), (clk_divider_flags), (table),      \
795  * devm_clk_hw_register_divider - register a divider clock with the clock framework
796  * @dev: device registering this clock
799  * @flags: framework-specific flags
802  * @width: width of the bitfield
803  * @clk_divider_flags: divider-specific flags for this clock
807 				width, clk_divider_flags, lock)		      \  argument
809 				  NULL, (flags), (reg), (shift), (width),     \
812  * devm_clk_hw_register_divider_table - register a table based divider clock
814  * @dev: device registering this clock
817  * @flags: framework-specific flags
820  * @width: width of the bitfield
821  * @clk_divider_flags: divider-specific flags for this clock
826 					   reg, shift, width,		      \  argument
830 				       (width), (clk_divider_flags), (table), \
837  * struct clk_mux - multiplexer clock
839  * @hw:		handle between common and hardware-specific interfaces
844  * @flags:	hardware-specific flags
851  * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
852  * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
853  * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
854  *	register, and mask of mux bits are in higher 16-bit of this register.
855  *	While setting the mux bits, higher 16-bit should also be updated to
857  * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
859  * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
861  * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
887 struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
894 struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np,
901 struct clk *clk_register_mux_table(struct device *dev, const char *name,
907 			 shift, width, clk_mux_flags, lock)		      \  argument
909 			       (flags), (reg), (shift), BIT((width)) - 1,     \
919 			    shift, width, clk_mux_flags, lock)		      \  argument
922 			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
925 				reg, shift, width, clk_mux_flags, lock)	      \  argument
928 			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
930 					flags, reg, shift, width,	      \  argument
934 			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
936 			    shift, width, clk_mux_flags, lock)		      \  argument
939 			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
952  * struct clk_fixed_factor - fixed multiplier and divider clock
954  * @hw:		handle between common and hardware-specific interfaces
972 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
976 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
980 struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
984  * struct clk_fractional_divider - adjustable fractional divider clock
986  * @hw:		handle between common and hardware-specific interfaces
989  * @mwidth:	width of the numerator bit field
991  * @nwidth:	width of the denominator bit field
997  * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
1001  * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
1004  * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
1009  *	caller's side the power-of-two capable prescaler exists.
1033 struct clk *clk_register_fractional_divider(struct device *dev,
1037 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
1044  * struct clk_multiplier - adjustable multiplier clock
1046  * @hw:		handle between common and hardware-specific interfaces
1049  * @width:	width of the multiplier bit field
1056  * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1061  * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1063  * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1071 	u8		width;  member
1085  * struct clk_composite - aggregate clock of mux, divider and gate clocks
1087  * @hw:		handle between common and hardware-specific interfaces
1088  * @mux_hw:	handle between composite and hardware-specific mux clock
1089  * @rate_hw:	handle between composite and hardware-specific rate clock
1090  * @gate_hw:	handle between composite and hardware-specific gate clock
1110 struct clk *clk_register_composite(struct device *dev, const char *name,
1116 struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1123 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1129 struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1136 struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev,
1145 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1146 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1148 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
1149 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1153 void devm_clk_unregister(struct device *dev, struct clk *clk);
1156 void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
1171 struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
1205 	dst->clk = src->clk;  in __clk_hw_set_clk()
1206 	dst->core = src->core;  in __clk_hw_set_clk()
1212 				      u8 width, unsigned long flags)  in divider_round_rate()  argument
1215 					 rate, prate, table, width, flags);  in divider_round_rate()
1221 					 u8 width, unsigned long flags,  in divider_ro_round_rate()  argument
1225 					    rate, prate, table, width, flags,  in divider_ro_round_rate()
1248  * routines, one at of_clk_init(), and one at platform device probe
1394 int devm_of_clk_add_hw_provider(struct device *dev,
1399 void devm_of_clk_del_provider(struct device *dev);
1428 static inline int devm_of_clk_add_hw_provider(struct device *dev,  in devm_of_clk_add_hw_provider()
1436 static inline void devm_of_clk_del_provider(struct device *dev) {}  in devm_of_clk_del_provider()
1440 	return ERR_PTR(-ENOENT);  in of_clk_src_simple_get()
1445 	return ERR_PTR(-ENOENT);  in of_clk_hw_simple_get()
1450 	return ERR_PTR(-ENOENT);  in of_clk_src_onecell_get()
1455 	return ERR_PTR(-ENOENT);  in of_clk_hw_onecell_get()