Searched +full:designware +full:- +full:pcie (Results 1 – 25 of 70) sorted by relevance
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| /Linux-v5.10/drivers/pci/controller/dwc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare PCI Core Support"
23 bool "TI DRA7xx PCIe controller Host Mode"
31 Enables support for the PCIe controller in the DRA7xx SoC to work in
32 host mode. There are two instances of PCIe controller in DRA7xx.
34 host-specific features PCI_DRA7XX_HOST must be selected and in order
35 to enable device-specific features PCI_DRA7XX_EP must be selected.
36 This uses the DesignWare core.
39 bool "TI DRA7xx PCIe controller Endpoint Mode"
46 Enables support for the PCIe controller in the DRA7xx SoC to work in
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| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PCIE_DW) += pcie-designware.o
3 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
4 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
5 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
6 obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
7 obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
8 obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
9 obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
10 obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
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| D | pcie-designware-plat.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe RC driver for Synopsys DesignWare Core
5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
22 #include "pcie-designware.h"
49 pp->num_vectors = MAX_MSI_IRQS; in dw_plat_set_num_vectors()
89 dev_err(pci->dev, "UNKNOWN IRQ type\n"); in dw_plat_pcie_ep_raise_irq()
116 struct dw_pcie *pci = dw_plat_pcie->pci; in dw_plat_add_pcie_port()
117 struct pcie_port *pp = &pci->pp; in dw_plat_add_pcie_port()
118 struct device *dev = &pdev->dev; in dw_plat_add_pcie_port()
121 pp->irq = platform_get_irq(pdev, 1); in dw_plat_add_pcie_port()
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| /Linux-v5.10/Documentation/devicetree/bindings/pci/ |
| D | pci-keystone.txt | 1 TI Keystone PCIe interface
3 Keystone PCI host Controller is based on the Synopsys DesignWare PCI
4 hardware version 3.65. It shares common functions with the PCIe DesignWare
6 Documentation/devicetree/bindings/pci/designware-pcie.txt
8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
9 for the details of DesignWare DT bindings. Additional properties are
12 Required Properties:-
14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
15 Should be "ti,am654-pcie-rc" for RC on AM654x SoC
16 reg: Three register ranges as listed in the reg-names property
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| D | amlogic,meson-pcie.txt | 1 Amlogic Meson AXG DWC PCIE SoC controller
3 Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
4 It shares common functions with the PCIe DesignWare core driver and
6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
11 - compatible:
13 - "amlogic,axg-pcie" for AXG SoC Family
14 - "amlogic,g12a-pcie" for G12A SoC Family
16 - reg:
18 - reg-names: Must be
19 - "elbi" External local bus interface registers
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| D | qcom,pcie.txt | 3 - compatible:
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
9 - "qcom,pcie-apq8064" for apq8064
10 - "qcom,pcie-apq8084" for apq8084
11 - "qcom,pcie-msm8996" for msm8996 or apq8096
12 - "qcom,pcie-ipq4019" for ipq4019
13 - "qcom,pcie-ipq8074" for ipq8074
14 - "qcom,pcie-qcs404" for qcs404
15 - "qcom,pcie-sdm845" for sdm845
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| D | pcie-al.txt | 1 * Amazon Annapurna Labs PCIe host bridge
3 Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare
5 Documentation/devicetree/bindings/pci/designware-pcie.txt.
9 - compatible:
13 - "amazon,al-alpine-v2-pcie" for alpine_v2
14 - "amazon,al-alpine-v3-pcie" for alpine_v3
16 - reg:
18 Value type: <prop-encoded-array>
19 Definition: Register ranges as listed in the reg-names property
21 - reg-names:
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| D | samsung,exynos5440-pcie.txt | 1 * Samsung Exynos 5440 PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 - compatible: "samsung,exynos5440-pcie"
8 - reg: base addresses and lengths of the PCIe controller,
9 - reg-names : First name should be set to "elbi".
12 NOTE: When using the "config" property, reg-names must be set.
13 - interrupts: A list of interrupt outputs for level interrupt,
15 - phys: From PHY binding. Phandle for the generic PHY.
16 Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
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| D | hisilicon-pcie.txt | 1 HiSilicon Hip05 and Hip06 PCIe host bridge DT description
3 HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core.
4 It shares common functions with the PCIe DesignWare core driver and inherits
6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
11 - compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
12 - reg: Should contain rc_dbi, config registers location and length.
13 - reg-names: Must include the following entries:
15 "config": PCIe configuration space registers.
16 - msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
17 - port-id: Should be 0, 1, 2 or 3.
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| D | ti-pci.txt | 3 PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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| D | kirin-pcie.txt | 1 HiSilicon Kirin SoCs PCIe host DT description
3 Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
4 It shares common functions with the PCIe DesignWare core driver and
6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
11 - compatible:
12 "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
13 - reg: Should contain rc_dbi, apb, phy, config registers location and length.
14 - reg-names: Must include the following entries:
18 "config": PCIe configuration space registers.
19 - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
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| D | layerscape-pci.txt | 1 Freescale Layerscape PCIe controller
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 which is used to describe the PLL settings at the time of chip-reset.
10 register available in the Freescale PCIe controller register set,
11 which can allow determining the underlying DesignWare PCIe controller version
15 - compatible: should contain the platform identifier such as:
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
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| D | hisilicon-histb-pcie.txt | 1 HiSilicon STB PCIe host bridge DT description
3 The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core.
4 It shares common functions with the DesignWare PCIe core driver and inherits
6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
11 - compatible: Should be one of the following strings:
12 "hisilicon,hi3798cv200-pcie"
13 - reg: Should contain sysctl, rc_dbi, config registers location and length.
14 - reg-names: Must include the following entries:
15 "control": control registers of PCIe controller;
16 "rc-dbi": configuration space of PCIe controller;
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| D | socionext,uniphier-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe endpoint controller
10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/designware-pcie.txt.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - $ref: "pci-ep.yaml#"
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| D | uniphier-pcie.txt | 1 Socionext UniPhier PCIe host controller bindings
3 This describes the devicetree bindings for PCIe host controller implemented
6 UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
7 It shares common functions with the PCIe DesignWare core driver and inherits
9 Documentation/devicetree/bindings/pci/designware-pcie.txt.
12 - compatible: Should be "socionext,uniphier-pcie".
13 - reg: Specifies offset and length of the register set for the device.
14 According to the reg-names, appropriate register sets are required.
15 - reg-names: Must include the following entries:
16 "dbi" - controller configuration registers
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| D | designware-pcie.txt | 1 * Synopsys DesignWare PCIe interface
4 - compatible:
5 "snps,dw-pcie" for RC mode;
6 "snps,dw-pcie-ep" for EP mode;
7 - reg: For designware cores version < 4.80 contains the configuration
8 address space. For designware core version >= 4.80, contains
10 - reg-names: Must be "config" for the PCIe configuration space and "atu" for
15 - #address-cells: set to <3>
16 - #size-cells: set to <2>
17 - device_type: set to "pci"
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| D | axis,artpec6-pcie.txt | 1 * Axis ARTPEC-6 PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
11 - reg: base addresses and lengths of the PCIe controller (DBI),
13 - reg-names: Must include the following entries:
14 - "dbi"
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| D | pci-armada8k.txt | 1 * Marvell Armada 7K/8K PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 - compatible: "marvell,armada8k-pcie"
8 - reg: must contain two register regions
9 - the control register region
10 - the config space region
11 - reg-names:
12 - "ctrl" for the control register region
13 - "config" for the config space region
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| D | nvidia,tegra194-pcie.txt | 1 NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based)
3 This PCIe controller is based on the Synopsis Designware PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
9 - power-domains: A phandle to the node that controls power to the respective
10 PCIe controller and a specifier name for the PCIe controller. Following are
11 the specifiers for the different PCIe controllers
19 "include/dt-bindings/power/tegra194-powergate.h" file.
20 - reg: A list of physical base address and length pairs for each set of
21 controller registers. Must contain an entry for each entry in the reg-names
23 - reg-names: Must include the following entries:
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| D | fsl,imx6q-pcie.txt | 1 * Freescale i.MX6 PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 - compatible:
8 - "fsl,imx6q-pcie"
9 - "fsl,imx6sx-pcie",
10 - "fsl,imx6qp-pcie"
11 - "fsl,imx7d-pcie"
12 - "fsl,imx8mq-pcie"
13 - reg: base address and length of the PCIe controller
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| D | spear13xx-pcie.txt | 1 SPEAr13XX PCIe DT detail:
4 SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
8 - compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
9 - phys : phandle to PHY node associated with PCIe controller
10 - phy-names : must be "pcie-phy"
11 - All other definitions as per generic PCI bindings
14 - st,pcie-is-gen1 indicates that forced gen1 initialization is needed.
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| /Linux-v5.10/drivers/usb/dwc3/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 tristate "DesignWare USB3 DRD Core Support"
10 USB controller based on the DesignWare USB3 IP Core.
73 Recent Exynos5 SoCs ship with one DesignWare Core USB3 IP inside,
77 tristate "PCIe-based Platforms"
81 If you're using the DesignWare Core IP with a PCIe (but not HAPS
85 tristate "Synopsys PCIe-based HAPS Platforms"
89 If you're using the DesignWare Core IP with a Synopsys PCIe HAPS
125 STMicroelectronics SoCs with one DesignWare Core USB3 IP
136 Some Qualcomm SoCs use DesignWare Core IP for USB2/3
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| /Linux-v5.10/drivers/dma/dw-edma/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 tristate "Synopsys DesignWare eDMA controller driver"
9 Support the Synopsys DesignWare eDMA controller, normally
13 tristate "Synopsys DesignWare eDMA PCIe driver"
17 Provides a glue-logic between the Synopsys DesignWare
18 eDMA controller and an endpoint PCIe device. This also serves
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| /Linux-v5.10/arch/arm/boot/dts/ |
| D | spear1310.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
15 compatible = "st,spear-spics-gpio";
17 st-spics,peripcfg-reg = <0x3b0>;
18 st-spics,sw-enable-bit = <12>;
19 st-spics,cs-value-bit = <11>;
20 st-spics,cs-enable-mask = <3>;
21 st-spics,cs-enable-shift = <8>;
22 gpio-controller;
23 #gpio-cells = <2>;
27 compatible = "st,spear1310-miphy";
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| D | spear1340.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
16 compatible = "st,spear-spics-gpio";
18 st-spics,peripcfg-reg = <0x42c>;
19 st-spics,sw-enable-bit = <21>;
20 st-spics,cs-value-bit = <20>;
21 st-spics,cs-enable-mask = <3>;
22 st-spics,cs-enable-shift = <18>;
23 gpio-controller;
24 #gpio-cells = <2>;
29 compatible = "st,spear1340-miphy";
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