/Linux-v6.1/drivers/clk/hisilicon/ |
D | clkdivider-hi6220.c | 1 // SPDX-License-Identifier: GPL-2.0-only 11 #include <linux/clk-provider.h> 19 #define div_mask(width) ((1 << (width)) - 1) 22 * struct hi6220_clk_divider - divider clock for hi6220 24 * @hw: handle between common and hardware-specific interfaces 29 * @table: the div table that the divider supports 49 struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); in hi6220_clkdiv_recalc_rate() local 51 val = readl_relaxed(dclk->reg) >> dclk->shift; in hi6220_clkdiv_recalc_rate() 52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate() 54 return divider_recalc_rate(hw, parent_rate, val, dclk->table, in hi6220_clkdiv_recalc_rate() [all …]
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/Linux-v6.1/Documentation/devicetree/bindings/display/ |
D | solomon,ssd1307fb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Maxime Ripard <mripard@kernel.org> 11 - Javier Martinez Canillas <javierm@redhat.com> 17 - items: 18 - enum: 19 - solomon,ssd1305fb-i2c 20 - solomon,ssd1306fb-i2c 21 - solomon,ssd1307fb-i2c [all …]
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/Linux-v6.1/drivers/gpu/drm/sun4i/ |
D | sun4i_dotclock.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 9 #include <linux/clk-provider.h> 28 struct sun4i_dclk *dclk = hw_to_dclk(hw); in sun4i_dclk_disable() local 30 regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG, in sun4i_dclk_disable() 36 struct sun4i_dclk *dclk = hw_to_dclk(hw); in sun4i_dclk_enable() local 38 return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG, in sun4i_dclk_enable() 45 struct sun4i_dclk *dclk = hw_to_dclk(hw); in sun4i_dclk_is_enabled() local 48 regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val); in sun4i_dclk_is_enabled() 56 struct sun4i_dclk *dclk = hw_to_dclk(hw); in sun4i_dclk_recalc_rate() local [all …]
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/Linux-v6.1/arch/arm/boot/dts/ |
D | dra7xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 8 atl_clkin0_ck: clock-atl-clkin0 { 9 #clock-cells = <0>; 10 compatible = "ti,dra7-atl-clock"; 11 clock-output-names = "atl_clkin0_ck"; 15 atl_clkin1_ck: clock-atl-clkin1 { 16 #clock-cells = <0>; 17 compatible = "ti,dra7-atl-clock"; 18 clock-output-names = "atl_clkin1_ck"; 22 atl_clkin2_ck: clock-atl-clkin2 { [all …]
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/Linux-v6.1/drivers/clk/mvebu/ |
D | armada-39x.c | 1 // SPDX-License-Identifier: GPL-2.0 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 15 #include <linux/clk-provider.h> 21 * SARL[14:10] : Ratios between CPU, NBCLK, HCLK and DCLK. 88 { .id = A390_CPU_TO_DCLK, .name = "dclk" }, 92 void __iomem *sar, int id, int *mult, int *div) in armada_39x_get_clk_ratio() argument 97 *div = 2; in armada_39x_get_clk_ratio() 101 *div = 4; in armada_39x_get_clk_ratio() 105 *div = 2; in armada_39x_get_clk_ratio() [all …]
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/Linux-v6.1/drivers/clk/samsung/ |
D | clk-s3c2410-dclk.c | 1 // SPDX-License-Identifier: GPL-2.0-only 11 #include <linux/clk-provider.h> 14 #include <linux/platform_data/clk-s3c2410.h> 45 * Clock for output-parent selection in misccr 63 val = clkout->modify_misccr(0, 0) >> clkout->shift; in s3c24xx_clkout_get_parent() 64 val >>= clkout->shift; in s3c24xx_clkout_get_parent() 65 val &= clkout->mask; in s3c24xx_clkout_get_parent() 68 return -EINVAL; in s3c24xx_clkout_get_parent() 77 clkout->modify_misccr((clkout->mask << clkout->shift), in s3c24xx_clkout_set_parent() 78 (index << clkout->shift)); in s3c24xx_clkout_set_parent() [all …]
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/Linux-v6.1/drivers/clk/ |
D | clk-lmk04832.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner 14 #include <linux/clk-provider.h> 24 /* 0x000 - 0x00d System Functions */ 36 /* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */ 77 /* 0x138 - 0x145 SYSREF, SYNC, and Device Config */ 126 /* 0x146 - 0x14a CLKin Control */ 136 /* 0x14b - 0x152 Holdover */ 138 /* 0x153 - 0x15f PLL1 Configuration */ 140 /* 0x160 - 0x16e PLL2 Configuration */ [all …]
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D | clk-ast2600.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 5 #define pr_fmt(fmt) "clk-ast2600: " fmt 14 #include <dt-bindings/clock/ast2600-clock.h> 16 #include "clk-aspeed.h" 65 [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */ 66 [ASPEED_CLK_GATE_ECLK] = { 1, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */ 67 [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */ 68 /* vclk parent - dclk/d1clk/hclk/mclk */ 69 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */ 70 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */ [all …]
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D | clk-aspeed.c | 1 // SPDX-License-Identifier: GPL-2.0+ 4 #define pr_fmt(fmt) "clk-aspeed: " fmt 13 #include <dt-bindings/clock/aspeed-clock.h> 15 #include "clk-aspeed.h" 49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */ 50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */ 51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */ 52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */ 53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */ 54 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */ [all …]
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D | clk-nomadik.c | 1 // SPDX-License-Identifier: GPL-2.0-only 4 * Copyright (C) 2013 ST-Ericsson AB 14 #include <linux/clk-provider.h> 74 pr_crit("force-enabling MXTALO\n"); in nomadik_clk_reboot_handler() 84 { .compatible = "stericsson,nomadik-src" }, 122 if (of_property_read_bool(np, "disable-sxtalo")) { in nomadik_src_init() 127 if (of_property_read_bool(np, "disable-mxtalo")) { in nomadik_src_init() 141 * struct clk_pll1 - Nomadik PLL1 clock 151 * struct clk_src - Nomadik src clock 174 if (pll->id == 1) { in pll_clk_enable() [all …]
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/Linux-v6.1/drivers/gpu/drm/radeon/ |
D | radeon_uvd.c | 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 72 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler); in radeon_uvd_init() 74 switch (rdev->family) { in radeon_uvd_init() 134 return -EINVAL; in radeon_uvd_init() 137 rdev->uvd.fw_header_present = false; in radeon_uvd_init() 138 rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES; in radeon_uvd_init() 141 r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev); in radeon_uvd_init() 143 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n", in radeon_uvd_init() 146 struct common_firmware_header *hdr = (void *)rdev->uvd_fw->data; in radeon_uvd_init() 149 r = radeon_ucode_validate(rdev->uvd_fw); in radeon_uvd_init() [all …]
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/Linux-v6.1/drivers/video/fbdev/ |
D | ssd1307fb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 122 array->type = type; in ssd1307fb_alloc_array() 136 dev_err(&client->dev, "Couldn't send I2C command.\n"); in ssd1307fb_write_array() 150 return -ENOMEM; in ssd1307fb_write_cmd() 152 array->data[0] = cmd; in ssd1307fb_write_cmd() 163 u8 col_end = col_start + cols - 1; in ssd1307fb_set_col_range() 166 if (col_start == par->col_start && col_end == par->col_end) in ssd1307fb_set_col_range() 169 ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_COL_RANGE); in ssd1307fb_set_col_range() 173 ret = ssd1307fb_write_cmd(par->client, col_start); in ssd1307fb_set_col_range() 177 ret = ssd1307fb_write_cmd(par->client, col_end); in ssd1307fb_set_col_range() [all …]
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/Linux-v6.1/drivers/gpu/drm/solomon/ |
D | ssd130x.c | 1 // SPDX-License-Identifier: GPL-2.0-only 138 return regmap_bulk_write(ssd130x->regmap, SSD130X_DATA, values, count); in ssd130x_write_data() 160 ret = regmap_write(ssd130x->regmap, SSD130X_COMMAND, value); in ssd130x_write_cmd() 163 } while (--count); in ssd130x_write_cmd() 175 u8 col_end = col_start + cols - 1; in ssd130x_set_col_range() 178 if (col_start == ssd130x->col_start && col_end == ssd130x->col_end) in ssd130x_set_col_range() 185 ssd130x->col_start = col_start; in ssd130x_set_col_range() 186 ssd130x->col_end = col_end; in ssd130x_set_col_range() 193 u8 page_end = page_start + pages - 1; in ssd130x_set_page_range() 196 if (page_start == ssd130x->page_start && page_end == ssd130x->page_end) in ssd130x_set_page_range() [all …]
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/Linux-v6.1/drivers/gpu/drm/amd/amdgpu/ |
D | si.c | 992 switch (adev->asic_type) { in si_query_video_codecs() 1014 return -EINVAL; in si_query_video_codecs() 1023 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in si_pcie_rreg() 1027 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in si_pcie_rreg() 1035 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in si_pcie_wreg() 1040 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in si_pcie_wreg() 1048 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in si_pciep_rreg() 1052 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in si_pciep_rreg() 1060 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in si_pciep_wreg() 1065 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in si_pciep_wreg() [all …]
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/Linux-v6.1/arch/arm/common/ |
D | sa1111.c | 1 // SPDX-License-Identifier: GPL-2.0-only 25 #include <linux/dma-map-ops.h> 30 #include <asm/mach-types.h> 107 int irq_base; /* base for cascaded on-chip IRQs */ 199 return irq_create_mapping(sachip->irqdomain, hwirq); in sa1111_map_irq() 212 void __iomem *mapbase = sachip->base + SA1111_INTC; in sa1111_irq_handler() 219 desc->irq_data.chip->irq_ack(&desc->irq_data); in sa1111_irq_handler() 228 irqdomain = sachip->irqdomain; in sa1111_irq_handler() 238 /* For level-based interrupts */ in sa1111_irq_handler() 239 desc->irq_data.chip->irq_unmask(&desc->irq_data); in sa1111_irq_handler() [all …]
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/Linux-v6.1/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
D | smu13_driver_if_v13_0_0.h | 499 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 502 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 824 uint16_t InitDclk; //assume same DCLK/VCLK for both instances 996 …uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vse… 997 …uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vse… 998 …uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be … 999 …uint16_t Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be … 1000 uint16_t Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Worst-case aging margin 1006 …//Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across… 1105 …uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. [all …]
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D | smu13_driver_if_v13_0_7.h | 503 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 506 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 862 uint16_t InitDclk; //assume same DCLK/VCLK for both instances 1034 …uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vse… 1035 …uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vse… 1036 …uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be … 1037 …uint16_t Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be … 1038 uint16_t Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Worst-case aging margin 1044 …//Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across… 1141 …uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. [all …]
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/Linux-v6.1/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
D | vegam_smumgr.c | 88 return -ENOMEM; in vegam_smu_init() 90 hwmgr->smu_backend = smu_data; in vegam_smu_init() 94 return -EINVAL; in vegam_smu_init() 108 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in vegam_start_smu_in_protection_mode() 116 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0); in vegam_start_smu_in_protection_mode() 118 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in vegam_start_smu_in_protection_mode() 121 /* De-assert reset */ in vegam_start_smu_in_protection_mode() 122 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in vegam_start_smu_in_protection_mode() 137 if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in vegam_start_smu_in_protection_mode() 139 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1); in vegam_start_smu_in_protection_mode() [all …]
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D | fiji_smumgr.c | 107 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode() 115 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode() 118 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode() 121 /* De-assert reset */ in fiji_start_smu_in_protection_mode() 122 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode() 130 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode() 134 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode() 147 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode() 150 "SMU Firmware start failed!", return -1); in fiji_start_smu_in_protection_mode() 169 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_non_protection_mode() [all …]
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D | polaris10_smumgr.c | 99 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); in polaris10_perform_btc() 101 if (0 != smu_data->avfs_btc_param) { in polaris10_perform_btc() 102 …if (0 != smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param, in polaris10_perform_btc() 105 result = -1; in polaris10_perform_btc() 108 if (smu_data->avfs_btc_param > 1) { in polaris10_perform_btc() 109 /* Soft-Reset to reset the engine before loading uCode */ in polaris10_perform_btc() 111 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000); in polaris10_perform_btc() 113 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff); in polaris10_perform_btc() 114 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0); in polaris10_perform_btc() 135 return -1); in polaris10_setup_graphics_level_structure() [all …]
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D | tonga_smumgr.c | 102 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode() 110 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode() 114 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode() 117 /* De-assert reset */ in tonga_start_in_protection_mode() 118 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode() 122 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode() 126 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode() 142 if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, in tonga_start_in_protection_mode() 145 return -EINVAL; in tonga_start_in_protection_mode() 164 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_non_protection_mode() [all …]
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/Linux-v6.1/drivers/gpu/drm/amd/include/ |
D | atomfirmware.h | 6 * Description header file of general definitions for OS and pre-OS video drivers 31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the chan… 115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/ 116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication 201 #define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD" 244 …tom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios, 603 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt 604 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt 655 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip 656 …eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without A… [all …]
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/Linux-v6.1/arch/arm64/boot/dts/rockchip/ |
D | rk3328.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/rk3328-cru.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/pinctrl/rockchip.h> 11 #include <dt-bindings/power/rk3328-power.h> 12 #include <dt-bindings/soc/rockchip,boot-mode.h> 13 #include <dt-bindings/thermal/thermal.h> 18 interrupt-parent = <&gic>; [all …]
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