Lines Matching +full:dclk +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
14 #include <linux/platform_data/clk-s3c2410.h>
45 * Clock for output-parent selection in misccr
63 val = clkout->modify_misccr(0, 0) >> clkout->shift; in s3c24xx_clkout_get_parent()
64 val >>= clkout->shift; in s3c24xx_clkout_get_parent()
65 val &= clkout->mask; in s3c24xx_clkout_get_parent()
68 return -EINVAL; in s3c24xx_clkout_get_parent()
77 clkout->modify_misccr((clkout->mask << clkout->shift), in s3c24xx_clkout_set_parent()
78 (index << clkout->shift)); in s3c24xx_clkout_set_parent()
99 return ERR_PTR(-EINVAL); in s3c24xx_register_clkout()
104 return ERR_PTR(-ENOMEM); in s3c24xx_register_clkout()
112 clkout->shift = shift; in s3c24xx_register_clkout()
113 clkout->mask = mask; in s3c24xx_register_clkout()
114 clkout->hw.init = &init; in s3c24xx_register_clkout()
115 clkout->modify_misccr = pdata->modify_misccr; in s3c24xx_register_clkout()
117 ret = clk_hw_register(dev, &clkout->hw); in s3c24xx_register_clkout()
121 return &clkout->hw; in s3c24xx_register_clkout()
125 * dclk and clkout init
177 u32 dclk_con, div, cmp; in s3c24xx_dclk_update_cmp() local
179 spin_lock_irqsave(&s3c24xx_dclk->dclk_lock, flags); in s3c24xx_dclk_update_cmp()
181 dclk_con = readl_relaxed(s3c24xx_dclk->base); in s3c24xx_dclk_update_cmp()
183 div = ((dclk_con >> div_shift) & DCLKCON_DCLK_DIV_MASK) + 1; in s3c24xx_dclk_update_cmp()
184 cmp = ((div + 1) / 2) - 1; in s3c24xx_dclk_update_cmp()
189 writel_relaxed(dclk_con, s3c24xx_dclk->base); in s3c24xx_dclk_update_cmp()
191 spin_unlock_irqrestore(&s3c24xx_dclk->dclk_lock, flags); in s3c24xx_dclk_update_cmp()
225 s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base); in s3c24xx_dclk_suspend()
233 writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base); in s3c24xx_dclk_resume()
248 s3c24xx_dclk = devm_kzalloc(&pdev->dev, in s3c24xx_dclk_probe()
253 return -ENOMEM; in s3c24xx_dclk_probe()
255 clk_table = s3c24xx_dclk->clk_data.hws; in s3c24xx_dclk_probe()
257 s3c24xx_dclk->dev = &pdev->dev; in s3c24xx_dclk_probe()
258 s3c24xx_dclk->clk_data.num = DCLK_MAX_CLKS; in s3c24xx_dclk_probe()
260 spin_lock_init(&s3c24xx_dclk->dclk_lock); in s3c24xx_dclk_probe()
262 s3c24xx_dclk->base = devm_platform_ioremap_resource(pdev, 0); in s3c24xx_dclk_probe()
263 if (IS_ERR(s3c24xx_dclk->base)) in s3c24xx_dclk_probe()
264 return PTR_ERR(s3c24xx_dclk->base); in s3c24xx_dclk_probe()
267 platform_get_device_id(pdev)->driver_data; in s3c24xx_dclk_probe()
270 clk_table[MUX_DCLK0] = clk_hw_register_mux(&pdev->dev, "mux_dclk0", in s3c24xx_dclk_probe()
271 dclk_variant->mux_parent_names, in s3c24xx_dclk_probe()
272 dclk_variant->mux_num_parents, 0, in s3c24xx_dclk_probe()
273 s3c24xx_dclk->base, 1, 1, 0, in s3c24xx_dclk_probe()
274 &s3c24xx_dclk->dclk_lock); in s3c24xx_dclk_probe()
275 clk_table[MUX_DCLK1] = clk_hw_register_mux(&pdev->dev, "mux_dclk1", in s3c24xx_dclk_probe()
276 dclk_variant->mux_parent_names, in s3c24xx_dclk_probe()
277 dclk_variant->mux_num_parents, 0, in s3c24xx_dclk_probe()
278 s3c24xx_dclk->base, 17, 1, 0, in s3c24xx_dclk_probe()
279 &s3c24xx_dclk->dclk_lock); in s3c24xx_dclk_probe()
281 clk_table[DIV_DCLK0] = clk_hw_register_divider(&pdev->dev, "div_dclk0", in s3c24xx_dclk_probe()
282 "mux_dclk0", 0, s3c24xx_dclk->base, in s3c24xx_dclk_probe()
283 4, 4, 0, &s3c24xx_dclk->dclk_lock); in s3c24xx_dclk_probe()
284 clk_table[DIV_DCLK1] = clk_hw_register_divider(&pdev->dev, "div_dclk1", in s3c24xx_dclk_probe()
285 "mux_dclk1", 0, s3c24xx_dclk->base, in s3c24xx_dclk_probe()
286 20, 4, 0, &s3c24xx_dclk->dclk_lock); in s3c24xx_dclk_probe()
288 clk_table[GATE_DCLK0] = clk_hw_register_gate(&pdev->dev, "gate_dclk0", in s3c24xx_dclk_probe()
290 s3c24xx_dclk->base, 0, 0, in s3c24xx_dclk_probe()
291 &s3c24xx_dclk->dclk_lock); in s3c24xx_dclk_probe()
292 clk_table[GATE_DCLK1] = clk_hw_register_gate(&pdev->dev, "gate_dclk1", in s3c24xx_dclk_probe()
294 s3c24xx_dclk->base, 16, 0, in s3c24xx_dclk_probe()
295 &s3c24xx_dclk->dclk_lock); in s3c24xx_dclk_probe()
297 clk_table[MUX_CLKOUT0] = s3c24xx_register_clkout(&pdev->dev, in s3c24xx_dclk_probe()
298 "clkout0", dclk_variant->clkout0_parent_names, in s3c24xx_dclk_probe()
299 dclk_variant->clkout0_num_parents, 4, 7); in s3c24xx_dclk_probe()
300 clk_table[MUX_CLKOUT1] = s3c24xx_register_clkout(&pdev->dev, in s3c24xx_dclk_probe()
301 "clkout1", dclk_variant->clkout1_parent_names, in s3c24xx_dclk_probe()
302 dclk_variant->clkout1_num_parents, 8, 7); in s3c24xx_dclk_probe()
306 dev_err(&pdev->dev, "clock %d failed to register\n", i); in s3c24xx_dclk_probe()
322 dev_err(&pdev->dev, "failed to register aliases, %d\n", ret); in s3c24xx_dclk_probe()
326 s3c24xx_dclk->dclk0_div_change_nb.notifier_call = in s3c24xx_dclk_probe()
329 s3c24xx_dclk->dclk1_div_change_nb.notifier_call = in s3c24xx_dclk_probe()
332 ret = clk_notifier_register(clk_table[DIV_DCLK0]->clk, in s3c24xx_dclk_probe()
333 &s3c24xx_dclk->dclk0_div_change_nb); in s3c24xx_dclk_probe()
337 ret = clk_notifier_register(clk_table[DIV_DCLK1]->clk, in s3c24xx_dclk_probe()
338 &s3c24xx_dclk->dclk1_div_change_nb); in s3c24xx_dclk_probe()
345 clk_notifier_unregister(clk_table[DIV_DCLK0]->clk, in s3c24xx_dclk_probe()
346 &s3c24xx_dclk->dclk0_div_change_nb); in s3c24xx_dclk_probe()
358 struct clk_hw **clk_table = s3c24xx_dclk->clk_data.hws; in s3c24xx_dclk_remove()
361 clk_notifier_unregister(clk_table[DIV_DCLK1]->clk, in s3c24xx_dclk_remove()
362 &s3c24xx_dclk->dclk1_div_change_nb); in s3c24xx_dclk_remove()
363 clk_notifier_unregister(clk_table[DIV_DCLK0]->clk, in s3c24xx_dclk_remove()
364 &s3c24xx_dclk->dclk0_div_change_nb); in s3c24xx_dclk_remove()
409 .name = "s3c2410-dclk",
412 .name = "s3c2412-dclk",
415 .name = "s3c2440-dclk",
418 .name = "s3c2443-dclk",
428 .name = "s3c24xx-dclk",