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/Linux-v6.1/drivers/dma/
Dtxx9dmac.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/dma-mapping.h>
24 static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc) in __dma_regs() argument
26 return dc->ch_regs; in __dma_regs()
30 const struct txx9dmac_chan *dc) in __dma_regs32() argument
32 return dc->ch_regs; in __dma_regs32()
35 #define channel64_readq(dc, name) \ argument
36 __raw_readq(&(__dma_regs(dc)->name))
37 #define channel64_writeq(dc, name, val) \ argument
38 __raw_writeq((val), &(__dma_regs(dc)->name))
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/Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.h2 * Copyright 2016-2020 Advanced Micro Devices, Inc.
32 struct dc;
34 void dcn10_hw_sequencer_construct(struct dc *dc);
38 struct dc *dc,
42 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
46 struct dc *dc);
48 struct dc *dc,
51 struct dc *dc,
54 struct dc *dc,
57 void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);
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Ddcn10_hw_sequencer.c65 hws->ctx
67 hws->regs->reg
71 hws->shifts->field_name, hws->masks->field_name
86 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
95 void dcn10_lock_all_pipes(struct dc *dc, in dcn10_lock_all_pipes() argument
103 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
104 pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes()
105 tg = pipe_ctx->stream_res.tg; in dcn10_lock_all_pipes()
111 if (pipe_ctx->top_pipe || in dcn10_lock_all_pipes()
112 !pipe_ctx->stream || in dcn10_lock_all_pipes()
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Ddcn10_resource.c27 #include "dc.h"
589 return &dpp->base; in dcn10_dpp_create()
605 return &ipp->base; in dcn10_ipp_create()
622 return &opp->base; in dcn10_opp_create()
639 ctx->dc->caps.extended_aux_timeout_support); in dcn10_aux_engine_create()
641 return &aux_engine->base; in dcn10_aux_engine_create()
690 return &mpc10->base; in dcn10_mpc_create()
701 hubbub1_construct(&dcn10_hubbub->base, ctx, in dcn10_hubbub_create()
706 return &dcn10_hubbub->base; in dcn10_hubbub_create()
719 tgn10->base.inst = instance; in dcn10_timing_generator_create()
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/Linux-v6.1/drivers/tty/
Dnozomi.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * nozomi.c -- HSDPA driver Broadband Wireless Data Card - Globe Trotter
18 * --------------------------------------------------------------------------
25 * --------------------------------------------------------------------------
78 if (tbuf[data_len - 2] == '\r') \
79 tbuf[data_len - 2] = 'r'; \
148 F32_2 = 2048, /* 512 bytes downlink + uplink * 2 -> 2048 */
149 F32_8 = 8192, /* 3072 bytes downl. + 1024 bytes uplink * 2 -> 8192 */
173 CTRL_ERROR = -1,
183 PORT_ERROR = -1,
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/Linux-v6.1/drivers/gpu/drm/amd/display/dc/core/
Ddc.c27 #include "dc.h"
82 dc->ctx
85 dc->ctx->logger
87 static const char DC_BUILD_ID[] = "production-build";
92 * DC is the OS-agnostic component of the amdgpu DC driver.
94 * DC maintains and validates a set of structs representing the state of the
97 * Main DC HW structs:
99 * struct dc - The central struct. One per driver. Created on driver load,
102 * struct dc_context - One per driver.
103 * Used as a backpointer by most other structs in dc.
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Ddc_stream.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
28 #include "dc.h"
35 #define DC_LOGGER dc->ctx->logger
42 if (sink->sink_signal == SIGNAL_TYPE_NONE) in update_stream_signal()
43 stream->signal = stream->link->connector_signal; in update_stream_signal()
45 stream->signal = sink->sink_signal; in update_stream_signal()
47 if (dc_is_dvi_signal(stream->signal)) { in update_stream_signal()
48 if (stream->ctx->dc->caps.dual_link_dvi && in update_stream_signal()
49 (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK && in update_stream_signal()
50 sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) in update_stream_signal()
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/Linux-v6.1/drivers/md/
Ddm-delay.c2 * Copyright (C) 2005-2007 Red Hat GmbH
16 #include <linux/device-mapper.h>
53 struct delay_c *dc = from_timer(dc, t, delay_timer); in handle_delayed_timer() local
55 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer()
58 static void queue_timeout(struct delay_c *dc, unsigned long expires) in queue_timeout() argument
60 mutex_lock(&dc->timer_lock); in queue_timeout()
62 if (!timer_pending(&dc->delay_timer) || expires < dc->delay_timer.expires) in queue_timeout()
63 mod_timer(&dc->delay_timer, expires); in queue_timeout()
65 mutex_unlock(&dc->timer_lock); in queue_timeout()
73 n = bio->bi_next; in flush_bios()
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/Linux-v6.1/drivers/md/bcache/
Dwriteback.c1 // SPDX-License-Identifier: GPL-2.0
3 * background writeback - scan btree for dirty data and write it to the backing
22 if (c->gc_after_writeback != (BCH_ENABLE_AUTO_GC) || in update_gc_after_writeback()
23 c->gc_stats.in_use < BCH_AUTO_GC_DIRTY_THRESHOLD) in update_gc_after_writeback()
26 c->gc_after_writeback |= BCH_DO_AUTO_GC; in update_gc_after_writeback()
30 static uint64_t __calc_target_rate(struct cached_dev *dc) in __calc_target_rate() argument
32 struct cache_set *c = dc->disk.c; in __calc_target_rate()
36 * flash-only devices in __calc_target_rate()
38 uint64_t cache_sectors = c->nbuckets * c->cache->sb.bucket_size - in __calc_target_rate()
39 atomic_long_read(&c->flash_dev_dirty_sectors); in __calc_target_rate()
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Dsuper.c1 // SPDX-License-Identifier: GPL-2.0
3 * bcache setup/teardown code, and some metadata io - read a superblock and
66 unsigned int bucket_size = le16_to_cpu(s->bucket_size); in get_bucket_size()
68 if (sb->version >= BCACHE_SB_VERSION_CDEV_WITH_FEATURES) { in get_bucket_size()
72 max = sizeof(unsigned int) * BITS_PER_BYTE - 1; in get_bucket_size()
73 order = le16_to_cpu(s->bucket_size); in get_bucket_size()
84 le16_to_cpu(s->obso_bucket_size_hi) << 16; in get_bucket_size()
97 sb->first_bucket= le16_to_cpu(s->first_bucket); in read_super_common()
98 sb->nbuckets = le64_to_cpu(s->nbuckets); in read_super_common()
99 sb->bucket_size = get_bucket_size(sb, s); in read_super_common()
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Dwriteback.h1 /* SPDX-License-Identifier: GPL-2.0 */
53 for (i = 0; i < d->nr_stripes; i++) in bcache_dev_sectors_dirty()
54 ret += atomic_read(d->stripe_sectors_dirty + i); in bcache_dev_sectors_dirty()
62 do_div(offset, d->stripe_size); in offset_to_stripe()
64 /* d->nr_stripes is in range [1, INT_MAX] */ in offset_to_stripe()
65 if (unlikely(offset >= d->nr_stripes)) { in offset_to_stripe()
67 offset, d->nr_stripes); in offset_to_stripe()
68 return -EINVAL; in offset_to_stripe()
78 static inline bool bcache_dev_stripe_dirty(struct cached_dev *dc, in bcache_dev_stripe_dirty() argument
82 int stripe = offset_to_stripe(&dc->disk, offset); in bcache_dev_stripe_dirty()
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/Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_hwseq.c58 hws->ctx
60 hws->regs->reg
62 dc->ctx->logger
67 hws->shifts->field_name, hws->masks->field_name
69 static void enable_memory_low_power(struct dc *dc) in enable_memory_low_power() argument
71 struct dce_hwseq *hws = dc->hwseq; in enable_memory_low_power()
74 if (dc->debug.enable_mem_low_power.bits.dmcu) { in enable_memory_low_power()
76 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { in enable_memory_low_power()
82 if (dc->debug.enable_mem_low_power.bits.optc) { in enable_memory_low_power()
87 if (dc->debug.enable_mem_low_power.bits.vga) { in enable_memory_low_power()
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/Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_hwseq.c62 hws->ctx
64 hws->regs->reg
66 dc->ctx->logger
71 hws->shifts->field_name, hws->masks->field_name
76 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut()
80 if (plane_state->blend_tf) { in dcn30_set_blend_lut()
81 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) in dcn30_set_blend_lut()
82 blend_lut = &plane_state->blend_tf->pwl; in dcn30_set_blend_lut()
83 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { in dcn30_set_blend_lut()
85 plane_state->blend_tf, &dpp_base->regamma_params, false); in dcn30_set_blend_lut()
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/Linux-v6.1/drivers/gpu/drm/amd/display/dc/dml/calcs/
Ddcn_calcs.c28 #include "dc.h"
40 dc->ctx->logger
50 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
54 * remain as-is as it provides us with a guarantee from HW that it is correct.
70 * slow-slow corner + 10% margin with voltages aligned to FCLK.
305 input->src.is_hsplit = false; in pipe_ctx_to_e2e_pipe_params()
308 if (pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE || in pipe_ctx_to_e2e_pipe_params()
309 pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) { in pipe_ctx_to_e2e_pipe_params()
311 input->src.hsplit_grp = pipe->pipe_idx; in pipe_ctx_to_e2e_pipe_params()
312 } else if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) { in pipe_ctx_to_e2e_pipe_params()
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/Linux-v6.1/drivers/gpu/drm/amd/display/dc/dml/
DMakefile24 # Makefile for the 'utils' sub-component of DAL.
29 dml_ccflags := -mhard-float -msse
33 dml_ccflags := -mhard-float -maltivec
37 ifneq ($(call gcc-min-version, 70100),y)
45 # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
47 dml_ccflags += -mpreferred-stack-boundary=4
49 dml_ccflags += -msse2
54 frame_warn_flag := -Wframe-larger-than=2048
57 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
60 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
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/Linux-v6.1/drivers/gpu/drm/tegra/
Ddc.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
31 #include "dc.h"
42 stats->frames = 0; in tegra_dc_stats_reset()
43 stats->vblank = 0; in tegra_dc_stats_reset()
44 stats->underflow = 0; in tegra_dc_stats_reset()
45 stats->overflow = 0; in tegra_dc_stats_reset()
49 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
53 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
54 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
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Drgb.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include "dc.h"
18 struct tegra_dc *dc; member
80 static void tegra_dc_write_regs(struct tegra_dc *dc, in tegra_dc_write_regs() argument
87 tegra_dc_writel(dc, table[i].value, table[i].offset); in tegra_dc_write_regs()
95 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable)); in tegra_rgb_encoder_disable()
96 tegra_dc_commit(rgb->dc); in tegra_rgb_encoder_disable()
105 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable)); in tegra_rgb_encoder_enable()
108 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); in tegra_rgb_encoder_enable()
111 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1)); in tegra_rgb_encoder_enable()
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/Linux-v6.1/drivers/scsi/esas2r/
Desas2r_disc.c5 * Copyright (c) 2001-2013 ATTO Technology, Inc.
8 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
22 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
41 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
43 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
85 struct esas2r_sas_nvram *nvr = a->nvram; in esas2r_disc_initialize()
89 clear_bit(AF_DISC_IN_PROG, &a->flags); in esas2r_disc_initialize()
90 clear_bit(AF2_DEV_SCAN, &a->flags2); in esas2r_disc_initialize()
91 clear_bit(AF2_DEV_CNT_OK, &a->flags2); in esas2r_disc_initialize()
93 a->disc_start_time = jiffies_to_msecs(jiffies); in esas2r_disc_initialize()
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/Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.c63 hws->ctx
65 hws->regs->reg
69 hws->shifts->field_name, hws->masks->field_name
71 static int find_free_gsl_group(const struct dc *dc) in find_free_gsl_group() argument
73 if (dc->res_pool->gsl_groups.gsl_0 == 0) in find_free_gsl_group()
75 if (dc->res_pool->gsl_groups.gsl_1 == 0) in find_free_gsl_group()
77 if (dc->res_pool->gsl_groups.gsl_2 == 0) in find_free_gsl_group()
89 * - immediate flip: find first available GSL group if not already assigned
92 * - vsync flip: disable GSL if used
95 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
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/Linux-v6.1/drivers/gpu/drm/amd/display/dc/
Ddc_stream.h2 * Copyright 2012-14 Advanced Micro Devices, Inc.
89 /* source MPCC instance. for use by internally by dc */
247 /* Output from DC when stream state is committed or altered
248 * DC may only access these values during:
330 bool dc_update_planes_and_stream(struct dc *dc,
345 void dc_commit_updates_for_stream(struct dc *dc,
354 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream);
356 uint8_t dc_get_current_stream_count(struct dc *dc);
357 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
373 * being refactored properly to be dce-specific
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Ddc.h2 * Copyright 2012-14 Advanced Micro Devices, Inc.
102 // for example, 1080p -> 8K is 4.0, or 4000 raw value
110 // for example, 8K -> 1080p is 0.25, or 250 raw value
122 * DOC: color-management-caps
127 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
134 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
150 * struct dpp_color_caps - color pipeline capabilities for display pipe and
155 * just plain 256-entry lookup
164 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
165 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
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/Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_hwseq.c59 hws->ctx
61 hws->regs->reg
63 dc->ctx->logger
68 hws->shifts->field_name, hws->masks->field_name
79 if (hws->ctx->dc->debug.disable_dsc_power_gate) in dcn32_dsc_pg_control()
156 if (hws->ctx->dc->debug.disable_hubp_power_gate) in dcn32_hubp_pg_control()
185 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc) in dcn32_check_no_memory_request_for_cab() argument
189 /* First, check no-memory-request case */ in dcn32_check_no_memory_request_for_cab()
190 for (i = 0; i < dc->current_state->stream_count; i++) { in dcn32_check_no_memory_request_for_cab()
191 if (dc->current_state->stream_status[i].plane_count) in dcn32_check_no_memory_request_for_cab()
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/Linux-v6.1/drivers/clk/mvebu/
Ddove-divider.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
15 #include "dove-divider.h"
51 static unsigned int dove_get_divider(struct dove_clk *dc) in dove_get_divider() argument
56 val = readl_relaxed(dc->base + DIV_CTRL0); in dove_get_divider()
57 val >>= dc->div_bit_start; in dove_get_divider()
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
61 if (dc->divider_table) in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
67 static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate, in dove_calc_divider() argument
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/Linux-v6.1/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddcn20_fpu.h1 /* SPDX-License-Identifier: MIT */
31 void dcn20_populate_dml_writeback_from_context(struct dc *dc,
39 void dcn20_calculate_dlg_params(struct dc *dc,
44 int dcn20_populate_dml_pipes_from_context(struct dc *dc,
48 void dcn20_calculate_wm(struct dc *dc,
57 void dcn20_update_bounding_box(struct dc *dc,
62 void dcn20_patch_bounding_box(struct dc *dc,
64 bool dcn20_validate_bandwidth_fp(struct dc *dc,
76 int dcn21_populate_dml_pipes_from_context(struct dc *dc,
80 bool dcn21_validate_bandwidth_fp(struct dc *dc,
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/Linux-v6.1/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c27 #include "dc.h"
75 * For eDP, after power-up/power/down,
85 hws->ctx
90 hws->regs->reg
94 hws->shifts->field_name, hws->masks->field_name
102 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
105 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
108 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
111 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
204 struct dc *dc, in dce110_enable_display_power_gating() argument
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