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/Linux-v5.15/arch/arm/boot/dts/
Drk322x.dtsi7 #include <dt-bindings/clock/rk3228-cru.h>
32 resets = <&cru SRST_CORE0>;
36 clocks = <&cru ARMCLK>;
44 resets = <&cru SRST_CORE1>;
54 resets = <&cru SRST_CORE2>;
64 resets = <&cru SRST_CORE3>;
140 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
153 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
163 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
177 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
[all …]
Drk3288.dtsi7 #include <dt-bindings/clock/rk3288-cru.h>
61 resets = <&cru SRST_CORE0>;
65 clocks = <&cru ARMCLK>;
72 resets = <&cru SRST_CORE1>;
76 clocks = <&cru ARMCLK>;
83 resets = <&cru SRST_CORE2>;
87 clocks = <&cru ARMCLK>;
94 resets = <&cru SRST_CORE3>;
98 clocks = <&cru ARMCLK>;
199 clocks = <&cru PCLK_TIMER>, <&xin24m>;
[all …]
Drk3xxx.dtsi42 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
44 assigned-clocks = <&cru ACLK_GPU>;
46 resets = <&cru SRST_GPU>;
56 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
57 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
78 clocks = <&cru CORE_PERI>;
85 clocks = <&cru CORE_PERI>;
103 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
114 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
162 clocks = <&cru HCLK_OTG0>;
[all …]
Drk3066a.dtsi9 #include <dt-bindings/clock/rk3066a-cru.h>
37 clocks = <&cru ARMCLK>;
69 clocks = <&cru ACLK_LCDC0>,
70 <&cru DCLK_LCDC0>,
71 <&cru HCLK_LCDC0>;
74 resets = <&cru SRST_LCDC0_AXI>,
75 <&cru SRST_LCDC0_AHB>,
76 <&cru SRST_LCDC0_DCLK>;
95 clocks = <&cru ACLK_LCDC1>,
96 <&cru DCLK_LCDC1>,
[all …]
Drk3036.dtsi7 #include <dt-bindings/clock/rk3036-cru.h>
41 resets = <&cru SRST_CORE0>;
47 clocks = <&cru ARMCLK>;
54 resets = <&cru SRST_CORE1>;
111 assigned-clocks = <&cru SCLK_GPU>;
113 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
116 resets = <&cru SRST_GPU>;
125 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
135 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
145 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
[all …]
Drv1108.dtsi6 #include <dt-bindings/clock/rv1108-cru.h>
36 clocks = <&cru ARMCLK>;
101 clocks = <&cru ACLK_DMAC>;
121 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
136 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
151 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
165 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
179 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
193 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
205 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
[all …]
Drk3188.dtsi9 #include <dt-bindings/clock/rk3188-cru.h>
27 clocks = <&cru ARMCLK>;
29 resets = <&cru SRST_CORE0>;
37 resets = <&cru SRST_CORE1>;
45 resets = <&cru SRST_CORE2>;
53 resets = <&cru SRST_CORE3>;
119 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
122 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
136 clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
139 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
[all …]
/Linux-v5.15/arch/arm64/boot/dts/rockchip/
Drk3399.dtsi6 #include <dt-bindings/clock/rk3399-cru.h>
75 clocks = <&cru ARMCLKL>;
87 clocks = <&cru ARMCLKL>;
99 clocks = <&cru ARMCLKL>;
111 clocks = <&cru ARMCLKL>;
123 clocks = <&cru ARMCLKB>;
135 clocks = <&cru ARMCLKB>;
211 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
212 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
232 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
[all …]
Drk3328.dtsi6 #include <dt-bindings/clock/rk3328-cru.h>
42 clocks = <&cru ARMCLK>;
55 clocks = <&cru ARMCLK>;
68 clocks = <&cru ARMCLK>;
81 clocks = <&cru ARMCLK>;
215 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
227 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
239 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
251 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
264 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
[all …]
Drk3568.dtsi6 #include <dt-bindings/clock/rk3568-cru.h>
226 cru: clock-controller@fdd20000 { label
227 compatible = "rockchip,rk3568-cru";
264 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
265 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
269 resets = <&cru SRST_SDMMC2>;
278 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
279 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
283 resets = <&cru SRST_SDMMC0>;
292 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
[all …]
Dpx30.dtsi6 #include <dt-bindings/clock/px30-cru.h>
47 clocks = <&cru ARMCLK>;
59 clocks = <&cru ARMCLK>;
71 clocks = <&cru ARMCLK>;
83 clocks = <&cru ARMCLK>;
249 clocks = <&cru HCLK_HOST>,
250 <&cru HCLK_OTG>,
251 <&cru SCLK_OTG_ADP>;
257 clocks = <&cru HCLK_SDMMC>,
258 <&cru SCLK_SDMMC>;
[all …]
Drk3368.dtsi6 #include <dt-bindings/clock/rk3368-cru.h>
182 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
183 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
187 resets = <&cru SRST_MMC0>;
196 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
197 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
201 resets = <&cru SRST_SDIO0>;
210 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
211 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
215 resets = <&cru SRST_EMMC>;
[all …]
Drk3308.dtsi7 #include <dt-bindings/clock/rk3308-cru.h>
46 clocks = <&cru ARMCLK>;
189 assigned-clocks = <&cru USB480M>;
191 clocks = <&cru SCLK_USBPHY_REF>;
233 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
246 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
259 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
272 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
285 clocks = <&cru PCLK_WDT>;
294 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/phy/
Dphy-rockchip-typec.txt11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
12 <&cru SCLK_UPHY1_TCPDCORE>;
43 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
44 <&cru SCLK_UPHY0_TCPDPHY_REF>;
46 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
48 resets = <&cru SRST_UPHY0>,
49 <&cru SRST_UPHY0_PIPE_L00>,
50 <&cru SRST_P_UPHY0_TCPHY>;
67 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
68 <&cru SCLK_UPHY1_TCPDPHY_REF>;
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/clock/
Drockchip,rk3128-cru.txt9 - compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru"
10 "rockchip,rk3126-cru" - controller compatible with RK3126 SoC.
11 "rockchip,rk3128-cru" - controller compatible with RK3128 SoC.
24 preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be
39 cru: cru@20000000 {
40 compatible = "rockchip,rk3128-cru";
56 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
Drockchip,rk3188-cru.txt9 - compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
10 "rockchip,rk3066a-cru"
23 preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
24 dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
42 cru: cru@20000000 {
43 compatible = "rockchip,rk3188-cru";
60 clocks = <&cru SCLK_UART0>;
Drockchip,px30-cru.txt9 - compatible: PMU for CRU should be "rockchip,px30-pmu-cru"
10 - compatible: CRU should be "rockchip,px30-cru"
16 - "xin24m" for both PMUCRU and CRU
17 - "gpll" for CRU (sourced from PMUCRU)
28 preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
51 cru: clock-controller@ff2b0000 {
52 compatible = "rockchip,px30-cru";
Drockchip,rk3308-cru.txt9 - compatible: CRU should be "rockchip,rk3308-cru"
22 preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
40 cru: clock-controller@ff500000 {
41 compatible = "rockchip,rk3308-cru";
55 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
/Linux-v5.15/Documentation/devicetree/bindings/pci/
Drockchip-pcie-ep.txt45 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
46 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
53 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
54 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
55 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
Drockchip-pcie-host.txt85 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
86 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
94 assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
95 assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
104 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
105 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
106 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
/Linux-v5.15/Documentation/devicetree/bindings/net/
Drockchip-dwmac.yaml105 #include <dt-bindings/clock/rk3288-cru.h>
112 clocks = <&cru SCLK_MAC>,
113 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
114 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
115 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
120 assigned-clocks = <&cru SCLK_MAC>;
/Linux-v5.15/Documentation/devicetree/bindings/media/
Drockchip-rga.yaml67 #include <dt-bindings/clock/rk3399-cru.h>
74 clocks = <&cru ACLK_RGA>,
75 <&cru HCLK_RGA>,
76 <&cru SCLK_RGA_CORE>;
79 resets = <&cru SRST_RGA_CORE>,
80 <&cru SRST_A_RGA>,
81 <&cru SRST_H_RGA>;
/Linux-v5.15/Documentation/devicetree/bindings/mmc/
Dsnps,dwcmshc-sdhci.yaml67 clocks = <&cru 17>, <&cru 18>, <&cru 19>, <&cru 20>, <&cru 21>;
78 clocks = <&cru 17>, <&cru 18>;
/Linux-v5.15/Documentation/devicetree/bindings/power/
Drockchip,power-controller.yaml148 #include <dt-bindings/clock/rk3399-cru.h>
203 clocks = <&cru ACLK_IEP>,
204 <&cru HCLK_IEP>;
210 clocks = <&cru ACLK_RGA>,
211 <&cru HCLK_RGA>;
218 clocks = <&cru ACLK_VCODEC>,
219 <&cru HCLK_VCODEC>;
225 clocks = <&cru ACLK_VDU>,
226 <&cru HCLK_VDU>;
239 clocks = <&cru ACLK_HDCP>,
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/mfd/
Dbrcm,cru.yaml4 $id: http://devicetree.org/schemas/mfd/brcm,cru.yaml#
7 title: Broadcom CRU
13 Broadcom CRU ("Clock and Reset Unit" or "Central Resource Unit") is a hardware
21 - brcm,ns-cru
25 description: CRU registers
52 cru-bus@1800c100 {
53 compatible = "brcm,ns-cru", "simple-mfd";

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