Lines Matching full:cru
7 #include <dt-bindings/clock/rk3228-cru.h>
32 resets = <&cru SRST_CORE0>;
36 clocks = <&cru ARMCLK>;
44 resets = <&cru SRST_CORE1>;
54 resets = <&cru SRST_CORE2>;
64 resets = <&cru SRST_CORE3>;
140 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
153 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
163 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
177 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
202 clocks = <&cru ACLK_HDCP>,
203 <&cru SCLK_HDCP>,
204 <&cru ACLK_IEP>,
205 <&cru HCLK_IEP>,
206 <&cru ACLK_RGA>,
207 <&cru HCLK_RGA>,
208 <&cru SCLK_RGA>;
218 clocks =<&cru ACLK_VOP>,
219 <&cru DCLK_VOP>,
220 <&cru HCLK_VOP>;
227 clocks = <&cru ACLK_VPU>,
228 <&cru HCLK_VPU>;
235 clocks = <&cru ACLK_RKVDEC>,
236 <&cru HCLK_RKVDEC>,
237 <&cru SCLK_VDEC_CABAC>,
238 <&cru SCLK_VDEC_CORE>;
246 clocks = <&cru ACLK_GPU>;
255 clocks = <&cru SCLK_OTGPHY0>;
282 clocks = <&cru SCLK_OTGPHY1>;
309 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
323 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
337 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
349 clocks = <&cru PCLK_EFUSE_256>;
370 clocks = <&cru PCLK_I2C0>;
383 clocks = <&cru PCLK_I2C1>;
396 clocks = <&cru PCLK_I2C2>;
409 clocks = <&cru PCLK_I2C3>;
421 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
432 clocks = <&cru PCLK_CPU>;
440 clocks = <&cru PCLK_PWM>;
450 clocks = <&cru PCLK_PWM>;
460 clocks = <&cru PCLK_PWM>;
470 clocks = <&cru PCLK_PWM>;
480 clocks = <&xin24m>, <&cru PCLK_TIMER>;
484 cru: clock-controller@110e0000 { label
485 compatible = "rockchip,rk3228-cru";
491 <&cru PLL_GPLL>, <&cru ARMCLK>,
492 <&cru PLL_CPLL>, <&cru ACLK_PERI>,
493 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
494 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
495 <&cru PCLK_CPU>;
511 clocks = <&cru ACLK_DMAC>;
565 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
567 assigned-clocks = <&cru SCLK_TSADC>;
569 resets = <&cru SRST_TSADC>;
583 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
606 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
609 resets = <&cru SRST_GPU_A>;
619 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
629 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
639 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
640 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
642 assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
652 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
662 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
664 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
685 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
696 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
699 resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
707 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
719 assigned-clocks = <&cru SCLK_HDMI_PHY>;
721 clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>;
725 resets = <&cru SRST_HDMI_P>;
748 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
749 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
761 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
762 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
776 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
777 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
784 resets = <&cru SRST_EMMC>;
794 clocks = <&cru HCLK_OTG>;
809 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
819 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
829 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
839 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
849 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
859 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
870 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
871 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
872 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
873 <&cru PCLK_GMAC>;
878 resets = <&cru SRST_GMAC>;
953 clocks = <&cru PCLK_GPIO0>;
966 clocks = <&cru PCLK_GPIO1>;
979 clocks = <&cru PCLK_GPIO2>;
992 clocks = <&cru PCLK_GPIO3>;