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/Linux-v5.15/tools/testing/selftests/rseq/
Dparam_test.c1 // SPDX-License-Identifier: LGPL-2.1
47 static __thread __attribute__((tls_model("initial-exec")))
52 static __thread __attribute__((tls_model("initial-exec"), unused))
116 "ahi %%" INJECT_ASM_REG ", -1\n\t" \
207 "addiu " INJECT_ASM_REG ", -1\n\t" \
225 if (loc_nr_loops == -1 && opt_modulo) { \
226 if (yield_mod_cnt == opt_modulo - 1) { \
301 intptr_t offset; member
318 intptr_t offset; member
327 /* A simple percpu spinlock. Grabs lock on current cpu. */
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/Linux-v5.15/arch/arm/mach-zynq/
Dslcr.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011-2013 Xilinx Inc.
19 #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
34 * zynq_slcr_write - Write to a register in SLCR block
37 * @offset: Register offset in SLCR block
41 static int zynq_slcr_write(u32 val, u32 offset) in zynq_slcr_write() argument
43 return regmap_write(zynq_slcr_regmap, offset, val); in zynq_slcr_write()
47 * zynq_slcr_read - Read a register in SLCR block
50 * @offset: Register offset in SLCR block
54 static int zynq_slcr_read(u32 *val, u32 offset) in zynq_slcr_read() argument
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/Linux-v5.15/Documentation/core-api/
Dthis_cpu_ops.rst8 this_cpu operations are a way of optimizing access to per cpu
11 the cpu permanently stored the beginning of the per cpu area for a
14 this_cpu operations add a per cpu variable offset to the processor
15 specific per cpu base and encode that operation in the instruction
16 operating on the per cpu variable.
19 the offset and the operation on the data. Therefore it is not
24 Read-modify-write operations are of particular interest. Frequently
32 synchronization is not necessary since we are dealing with per cpu
37 Please note that accesses by remote processors to a per cpu area are
66 ------------------------------------
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/Linux-v5.15/drivers/gpio/
Dgpio-mvebu.c6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
22 * - the basic variant, called "orion-gpio", with the simplest
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
29 * - the armadaxp variant for Armada XP systems. This variant keeps
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
32 * registers n a separate memory area for the per-CPU GPIO
80 /* The MV78200 has per-CPU registers for edge mask and level mask */
81 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) argument
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/Linux-v5.15/arch/ia64/include/asm/uv/
Duv_hub.h23 * M - The low M bits of a physical address represent the offset
28 * N - Number of bits in the node portion of a socket physical
31 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
34 * right shift the NASID by 1 to exclude the always-zero bit.
37 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
40 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
45 * +--------------------------------+---------------------+
47 * +--------------------------------+---------------------+
48 * |<-------53 - M bits --->|<--------M bits ----->
50 * M - number of node offset bits (35 .. 40)
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/Linux-v5.15/kernel/time/
Dtimer_list.c1 // SPDX-License-Identifier: GPL-2.0
18 #include "tick-internal.h"
21 int cpu; member
28 * to the console (on SysRq-Q):
49 SEQ_printf(m, " #%d: <%pK>, %ps", idx, taddr, timer->function); in print_timer()
50 SEQ_printf(m, ", S:%02x", timer->state); in print_timer()
52 SEQ_printf(m, " # expires at %Lu-%Lu nsecs [in %Ld to %Ld nsecs]\n", in print_timer()
55 (long long)(ktime_to_ns(hrtimer_get_softexpires(timer)) - now), in print_timer()
56 (long long)(ktime_to_ns(hrtimer_get_expires(timer)) - now)); in print_timer()
73 raw_spin_lock_irqsave(&base->cpu_base->lock, flags); in print_active_timers()
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/Linux-v5.15/arch/x86/include/asm/uv/
Duv_hub.h9 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
33 * M - The low M bits of a physical address represent the offset
38 * N - Number of bits in the node portion of a socket physical
41 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
44 * right shift the NASID by 1 to exclude the always-zero bit.
47 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
50 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
53 * GPA - (global physical address) a socket physical address converted
62 * +--------------------------------+---------------------+
64 * +--------------------------------+---------------------+
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/Linux-v5.15/drivers/gpu/drm/i915/gem/selftests/
Di915_gem_coherency.c2 * SPDX-License-Identifier: MIT
23 static int cpu_set(struct context *ctx, unsigned long offset, u32 v) in cpu_set() argument
28 u32 *cpu; in cpu_set() local
31 i915_gem_object_lock(ctx->obj, NULL); in cpu_set()
32 err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush); in cpu_set()
36 page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); in cpu_set()
38 cpu = map + offset_in_page(offset); in cpu_set()
41 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
43 *cpu = v; in cpu_set()
46 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
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/Linux-v5.15/drivers/clk/qcom/
Dkrait-cc.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk-provider.h>
16 #include "clk-krait.h"
42 mux->old_index = krait_mux_clk_ops.get_parent(&mux->hw); in krait_notifier_cb()
43 ret = krait_mux_clk_ops.set_parent(&mux->hw, mux->safe_sel); in krait_notifier_cb()
44 mux->reparent = false; in krait_notifier_cb()
51 if (!mux->reparent) in krait_notifier_cb()
52 ret = krait_mux_clk_ops.set_parent(&mux->hw, in krait_notifier_cb()
53 mux->old_index); in krait_notifier_cb()
64 mux->clk_nb.notifier_call = krait_notifier_cb; in krait_notifier_register()
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/Linux-v5.15/drivers/gpu/drm/lima/
Dlima_vm.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
5 #include <linux/dma-mapping.h>
26 #define LIMA_VM_PT_MASK ((1 << LIMA_VM_PD_SHIFT) - 1)
27 #define LIMA_VM_BT_MASK ((1 << LIMA_VM_PB_SHIFT) - 1)
43 vm->bts[pbe].cpu[bte] = 0; in lima_vm_unmap_range()
52 if (!vm->bts[pbe].cpu) { in lima_vm_map_page()
57 vm->bts[pbe].cpu = dma_alloc_wc( in lima_vm_map_page()
58 vm->dev->dev, LIMA_PAGE_SIZE << LIMA_VM_NUM_PT_PER_BT_SHIFT, in lima_vm_map_page()
59 &vm->bts[pbe].dma, GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); in lima_vm_map_page()
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/Linux-v5.15/arch/arm/mach-hisi/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
23 void hi3xxx_set_cpu_jump(int cpu, void *jump_addr) in hi3xxx_set_cpu_jump() argument
25 cpu = cpu_logical_map(cpu); in hi3xxx_set_cpu_jump()
26 if (!cpu || !ctrl_base) in hi3xxx_set_cpu_jump()
28 writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2)); in hi3xxx_set_cpu_jump()
31 int hi3xxx_get_cpu_jump(int cpu) in hi3xxx_get_cpu_jump() argument
33 cpu = cpu_logical_map(cpu); in hi3xxx_get_cpu_jump()
34 if (!cpu || !ctrl_base) in hi3xxx_get_cpu_jump()
36 return readl_relaxed(ctrl_base + ((cpu - 1) << 2)); in hi3xxx_get_cpu_jump()
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/Linux-v5.15/Documentation/devicetree/bindings/timer/
Dqcom,msm-timer.txt5 - compatible : Should at least contain "qcom,msm-timer". More specific
8 "qcom,kpss-timer" - krait subsystem
9 "qcom,scss-timer" - scorpion subsystem
11 - interrupts : Interrupts for the debug timer, the first general purpose
15 - reg : Specifies the base address of the timer registers.
17 - clocks: Reference to the parent clocks, one per output clock. The parents
20 - clock-names: The name of the clocks as free-form strings. They should be in
23 - clock-frequency : The frequency of the debug timer and the general purpose
28 - cpu-offset : per-cpu offset used when the timer is accessed without the
29 CPU remapping facilities. The offset is
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/Linux-v5.15/drivers/media/pci/tw68/
Dtw68-risc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * acknowledged. Full credit goes to them - any problems within this code
25 * @sglist: pointer to "scatter-gather list" of buffer pointers
26 * @offset: offset to target memory buffer
27 * @sync_line: 0 -> no sync, 1 -> odd sync, 2 -> even sync
34 unsigned int offset, u32 sync_line, in tw68_risc_field() argument
57 while (offset && offset >= sg_dma_len(sg)) { in tw68_risc_field()
58 offset -= sg_dma_len(sg); in tw68_risc_field()
61 if (bpl <= sg_dma_len(sg) - offset) { in tw68_risc_field()
64 /* (offset<<12) |*/ bpl); in tw68_risc_field()
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/Linux-v5.15/kernel/sched/
Dstats.c1 // SPDX-License-Identifier: GPL-2.0
17 int cpu; in show_schedstat() local
28 cpu = (unsigned long)(v - 2); in show_schedstat()
29 rq = cpu_rq(cpu); in show_schedstat()
31 /* runqueue-specific stats */ in show_schedstat()
33 "cpu%d %u 0 %u %u %u %u %llu %llu %lu", in show_schedstat()
34 cpu, rq->yld_count, in show_schedstat()
35 rq->sched_count, rq->sched_goidle, in show_schedstat()
36 rq->ttwu_count, rq->ttwu_local, in show_schedstat()
37 rq->rq_cpu_time, in show_schedstat()
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/Linux-v5.15/include/linux/
Drelay.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2002, 2003 - Tom Zanussi (zanussi@us.ibm.com), IBM Corp
6 * Copyright (C) 1999, 2000, 2001, 2002 - Karim Yaghmour (karim@opersys.com)
32 * Per-cpu relay channel buffer
37 void *data; /* start of current sub-buffer */
38 size_t offset; /* current offset into sub-buffer */ member
39 size_t subbufs_produced; /* count of sub-buffers produced */
40 size_t subbufs_consumed; /* count of sub-buffers consumed */
49 size_t *padding; /* padding counts per sub-buffer */
53 unsigned int cpu; /* this buf's cpu */ member
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/Linux-v5.15/scripts/gdb/linux/
Dcpus.py4 # per-cpu tools
6 # Copyright (c) Siemens AG, 2011-2013
27 return gdb.selected_thread().num - 1
30 if tid > (0x100000000 - MAX_CPUS - 2):
31 return 0x100000000 - tid - 2
33 return tasks.get_thread_info(tasks.get_task_by_pid(tid))['cpu']
35 raise gdb.GdbError("Sorry, obtaining the current CPU is not yet "
39 def per_cpu(var_ptr, cpu): argument
40 if cpu == -1:
41 cpu = get_current_cpu()
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/Linux-v5.15/arch/x86/platform/uv/
Duv_nmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2007-2017 Silicon Graphics, Inc. All rights reserved.
10 #include <linux/cpu.h>
36 * Handle system-wide NMI events generated by the global 'power nmi' command.
38 * Basic operation is to field the NMI interrupt on each CPU and wait
39 * until all CPU's have arrived into the nmi handler. If some CPU's do not
49 * second (~4M/s for 1024 CPU threads). Our secondary NMI handler is
65 /* Non-zero indicates newer SMM NMI handler present */
82 #define PCH_PCR_GPIO_ADDRESS(offset) (int *)((u64)(pch_base) | (u64)(offset)) argument
90 static atomic_t uv_nmi_cpu = ATOMIC_INIT(-1);
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/Linux-v5.15/tools/perf/arch/arm/util/
Dcs-etm.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/coresight-pmu.h>
18 #include "cs-etm.h"
29 #include "../../../util/cs-etm.h"
59 static bool cs_etm_is_etmv4(struct auxtrace_record *itr, int cpu);
60 static bool cs_etm_is_ete(struct auxtrace_record *itr, int cpu);
63 struct evsel *evsel, int cpu) in cs_etm_set_context_id() argument
68 int err = -EINVAL; in cs_etm_set_context_id()
73 cs_etm_pmu = ptr->cs_etm_pmu; in cs_etm_set_context_id()
75 if (!cs_etm_is_etmv4(itr, cpu)) in cs_etm_set_context_id()
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/Linux-v5.15/tools/testing/selftests/vm/
Duserfaultfd.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * There are three threads running per CPU:
13 * 1) one per-CPU thread takes a per-page pthread_mutex in a random
15 * area_src), and increments a per-page counter in the same page,
18 * 2) another per-CPU thread handles the userfaults generated by
22 * 3) one last per-CPU thread transfers the memory in the background
24 * 2). Each cpu thread takes cares of transferring a portion of the
32 * per-CPU threads 1 by triggering userfaults inside
82 /* Whether to test uffd write-protection */
92 static int uffd = -1;
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/Linux-v5.15/arch/mips/boot/dts/mti/
Dsead3.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "mti,sead-3";
14 model = "MIPS SEAD-3";
17 stdout-path = "serial1:115200";
26 cpu@0 {
36 cpu_intc: interrupt-controller {
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/Linux-v5.15/drivers/crypto/cavium/nitrox/
Dnitrox_isr.c1 // SPDX-License-Identifier: GPL-2.0
15 * - NPS packet ring, AQMQ ring and ZQMQ ring
24 * nps_pkt_slc_isr - IRQ handler for NPS solicit port
32 struct nitrox_cmdq *cmdq = qvec->cmdq; in nps_pkt_slc_isr()
34 slc_cnts.value = readq(cmdq->compl_cnt_csr_addr); in nps_pkt_slc_isr()
37 tasklet_hi_schedule(&qvec->resp_tasklet); in nps_pkt_slc_isr()
56 unsigned long value, offset; in clear_nps_pkt_err_intr() local
64 offset = NPS_PKT_SLC_ERR_TYPE; in clear_nps_pkt_err_intr()
65 value = nitrox_read_csr(ndev, offset); in clear_nps_pkt_err_intr()
66 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
[all …]
/Linux-v5.15/drivers/macintosh/
Dwindfarm_pm121.c1 // SPDX-License-Identifier: GPL-2.0-only
16 * that none of the code has been re-used, it's a complete
17 * re-implementation
21 * controls with a tiny difference. The control-ids of hard-drive-fan
22 * and cpu-fan is swapped.
28 * new_min = ((((average_power * slope) >> 16) + offset) >> 16) + min_value
34 * offset : -19563152
38 * offset : -15650652
44 * offset : -15650652
48 * offset : -19563152
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/Linux-v5.15/Documentation/devicetree/bindings/arm/hisilicon/controller/
Dsysctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wei Xu <xuwei5@hisilicon.com>
19 offset. In addition, the HiP01 system controller has some specific control
23 Hisilicon system controller --> hisilicon,sysctrl
24 HiP01 system controller --> hisilicon,hip01-sysctrl
25 Hi6220 system controller --> hisilicon,hi6220-sysctrl
26 Hi3519 system controller --> hisilicon,hi3519-sysctrl
29 - if:
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/Linux-v5.15/tools/lib/traceevent/plugins/
Dplugin_function.c1 // SPDX-License-Identifier: LGPL-2.1
9 #include "event-parse.h"
10 #include "event-utils.h"
11 #include "trace-seq.h"
18 static int cpus = -1;
38 .name = "offset",
60 if (pos < stack->size) in add_child()
61 free(stack->stack[pos]); in add_child()
65 ptr = realloc(stack->stack, sizeof(char *) * in add_child()
66 (stack->size + STK_BLK)); in add_child()
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/Linux-v5.15/drivers/clocksource/
Dexynos_mct.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/arch/arm/mach-exynos4/mct.c
7 * Exynos4 MCT(Multi-Core Timer) support
15 #include <linux/cpu.h>
95 static void exynos4_mct_write(unsigned int value, unsigned long offset) in exynos4_mct_write() argument
101 writel_relaxed(value, reg_base + offset); in exynos4_mct_write()
103 if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) { in exynos4_mct_write()
104 stat_addr = (offset & EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET; in exynos4_mct_write()
105 switch (offset & ~EXYNOS4_MCT_L_MASK) { in exynos4_mct_write()
119 switch (offset) { in exynos4_mct_write()
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