1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/arch/arm/mach-exynos4/mct.c
7  * Exynos4 MCT(Multi-Core Timer) support
15 #include <linux/cpu.h>
95 static void exynos4_mct_write(unsigned int value, unsigned long offset)  in exynos4_mct_write()  argument
101 	writel_relaxed(value, reg_base + offset);  in exynos4_mct_write()
103 	if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {  in exynos4_mct_write()
104 		stat_addr = (offset & EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;  in exynos4_mct_write()
105 		switch (offset & ~EXYNOS4_MCT_L_MASK) {  in exynos4_mct_write()
119 		switch (offset) {  in exynos4_mct_write()
156 	panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);  in exynos4_mct_write()
170  * exynos4_read_count_64 - Read all 64-bits of the global counter
172  * This will read all 64-bits of the global counter taking care to make sure
174  * slow (hundreds of nanoseconds) so you should use the 32-bit (lower half
194  * exynos4_read_count_32 - Read the lower 32-bits of the global counter
196  * This will read just the lower 32-bits of the global counter.  This is marked
217 	.name		= "mct-frc",
236 			 "cycles_t needs to move to 32-bit for ARM64 usage");  in exynos4_read_current_timer()
310 	cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)  in mct_set_state_periodic()
311 			    >> evt->shift);  in mct_set_state_periodic()
318 	.name			= "mct-comp",
336 	evt->event_handler(evt);  in exynos4_mct_comp_isr()
361 	unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;  in exynos4_mct_tick_stop()  local
363 	tmp = readl_relaxed(reg_base + offset);  in exynos4_mct_tick_stop()
366 		exynos4_mct_write(tmp, offset);  in exynos4_mct_tick_stop()
380 	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);  in exynos4_mct_tick_start()
383 	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);  in exynos4_mct_tick_start()
385 	tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET);  in exynos4_mct_tick_start()
388 	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);  in exynos4_mct_tick_start()
394 	if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1)  in exynos4_mct_tick_clear()
395 		exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);  in exynos4_mct_tick_clear()
424 	cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)  in set_state_periodic()
425 			    >> evt->shift);  in set_state_periodic()
434 	struct clock_event_device *evt = &mevt->evt;  in exynos4_mct_tick_isr()
441 	if (!clockevent_state_periodic(&mevt->evt))  in exynos4_mct_tick_isr()
446 	evt->event_handler(evt);  in exynos4_mct_tick_isr()
451 static int exynos4_mct_starting_cpu(unsigned int cpu)  in exynos4_mct_starting_cpu()  argument
454 		per_cpu_ptr(&percpu_mct_tick, cpu);  in exynos4_mct_starting_cpu()
455 	struct clock_event_device *evt = &mevt->evt;  in exynos4_mct_starting_cpu()
457 	mevt->base = EXYNOS4_MCT_L_BASE(cpu);  in exynos4_mct_starting_cpu()
458 	snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);  in exynos4_mct_starting_cpu()
460 	evt->name = mevt->name;  in exynos4_mct_starting_cpu()
461 	evt->cpumask = cpumask_of(cpu);  in exynos4_mct_starting_cpu()
462 	evt->set_next_event = exynos4_tick_set_next_event;  in exynos4_mct_starting_cpu()
463 	evt->set_state_periodic = set_state_periodic;  in exynos4_mct_starting_cpu()
464 	evt->set_state_shutdown = set_state_shutdown;  in exynos4_mct_starting_cpu()
465 	evt->set_state_oneshot = set_state_shutdown;  in exynos4_mct_starting_cpu()
466 	evt->set_state_oneshot_stopped = set_state_shutdown;  in exynos4_mct_starting_cpu()
467 	evt->tick_resume = set_state_shutdown;  in exynos4_mct_starting_cpu()
468 	evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |  in exynos4_mct_starting_cpu()
470 	evt->rating = MCT_CLKEVENTS_RATING,  in exynos4_mct_starting_cpu()
472 	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);  in exynos4_mct_starting_cpu()
476 		if (evt->irq == -1)  in exynos4_mct_starting_cpu()
477 			return -EIO;  in exynos4_mct_starting_cpu()
479 		irq_force_affinity(evt->irq, cpumask_of(cpu));  in exynos4_mct_starting_cpu()
480 		enable_irq(evt->irq);  in exynos4_mct_starting_cpu()
490 static int exynos4_mct_dying_cpu(unsigned int cpu)  in exynos4_mct_dying_cpu()  argument
493 		per_cpu_ptr(&percpu_mct_tick, cpu);  in exynos4_mct_dying_cpu()
494 	struct clock_event_device *evt = &mevt->evt;  in exynos4_mct_dying_cpu()
496 	evt->set_state_shutdown(evt);  in exynos4_mct_dying_cpu()
498 		if (evt->irq != -1)  in exynos4_mct_dying_cpu()
499 			disable_irq_nosync(evt->irq);  in exynos4_mct_dying_cpu()
500 		exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);  in exynos4_mct_dying_cpu()
509 	int err, cpu;  in exynos4_timer_resources()  local
534 		for_each_possible_cpu(cpu) {  in exynos4_timer_resources()
535 			int mct_irq = mct_irqs[MCT_L0_IRQ + cpu];  in exynos4_timer_resources()
537 				per_cpu_ptr(&percpu_mct_tick, cpu);  in exynos4_timer_resources()
539 			pcpu_mevt->evt.irq = -1;  in exynos4_timer_resources()
545 					pcpu_mevt->name, pcpu_mevt)) {  in exynos4_timer_resources()
546 				pr_err("exynos-mct: cannot register IRQ (cpu%d)\n",  in exynos4_timer_resources()
547 									cpu);  in exynos4_timer_resources()
551 			pcpu_mevt->evt.irq = mct_irq;  in exynos4_timer_resources()
555 	/* Install hotplug callbacks which configure the timer on this CPU */  in exynos4_timer_resources()
569 		for_each_possible_cpu(cpu) {  in exynos4_timer_resources()
571 				per_cpu_ptr(&percpu_mct_tick, cpu);  in exynos4_timer_resources()
573 			if (pcpu_mevt->evt.irq != -1) {  in exynos4_timer_resources()
574 				free_irq(pcpu_mevt->evt.irq, pcpu_mevt);  in exynos4_timer_resources()
575 				pcpu_mevt->evt.irq = -1;  in exynos4_timer_resources()
622 TIMER_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
623 TIMER_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);