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/Linux-v6.1/drivers/i2c/muxes/
Di2c-mux-gpmux.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/i2c-mux.h>
18 struct mux_control *control; member
28 ret = mux_control_select(mux->control, chan); in i2c_mux_select()
29 mux->do_not_deselect = ret < 0; in i2c_mux_select()
38 if (mux->do_not_deselect) in i2c_mux_deselect()
41 return mux_control_deselect(mux->control); in i2c_mux_deselect()
46 struct device_node *np = dev->of_node; in mux_parent_adapter()
48 struct i2c_adapter *parent; in mux_parent_adapter() local
50 parent_np = of_parse_phandle(np, "i2c-parent", 0); in mux_parent_adapter()
[all …]
/Linux-v6.1/drivers/iio/multiplexer/
Diio-mux.c1 // SPDX-License-Identifier: GPL-2.0
31 struct mux_control *control; member
32 struct iio_channel *parent; member
42 struct mux_child *child = &mux->child[idx]; in iio_mux_select()
43 struct iio_chan_spec const *chan = &mux->chan[idx]; in iio_mux_select()
47 ret = mux_control_select_delay(mux->control, chan->channel, in iio_mux_select()
48 mux->delay_us); in iio_mux_select()
50 mux->cached_state = -1; in iio_mux_select()
54 if (mux->cached_state == chan->channel) in iio_mux_select()
57 if (chan->ext_info) { in iio_mux_select()
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/Linux-v6.1/drivers/usb/musb/
Dsunxi.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/phy/phy-sun4i-usb.h>
95 if (!test_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags)) in sunxi_musb_work()
98 if (test_and_clear_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags)) { in sunxi_musb_work()
99 struct musb *musb = glue->musb; in sunxi_musb_work()
103 spin_lock_irqsave(&musb->lock, flags); in sunxi_musb_work()
105 devctl = readb(musb->mregs + SUNXI_MUSB_DEVCTL); in sunxi_musb_work()
106 if (test_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags)) { in sunxi_musb_work()
107 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); in sunxi_musb_work()
108 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; in sunxi_musb_work()
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Dmusb_dsps.c1 // SPDX-License-Identifier: GPL-2.0
21 #include <linux/dma-mapping.h>
25 #include <linux/platform_data/usb-omap.h>
47 u16 control; member
60 /* bit positions for control */
91 u32 control; member
119 { "control", 0x14 },
137 struct musb *musb = platform_get_drvdata(glue->musb); in dsps_mod_timer()
141 wait = msecs_to_jiffies(glue->wrp->poll_timeout); in dsps_mod_timer()
145 mod_timer(&musb->dev_timer, jiffies + wait); in dsps_mod_timer()
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/Linux-v6.1/Documentation/devicetree/bindings/mux/
Dreg-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/reg-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic register bitfield-based multiplexer controller bindings
10 - Peter Rosin <peda@axentia.se>
13 Define register bitfields to be used to control multiplexers. The parent
19 - reg-mux # parent device of mux controller is not syscon device
20 - mmio-mux # parent device of mux controller is syscon device
24 '#mux-control-cells':
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Dgpio-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/gpio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO-based multiplexer controller bindings
10 - Peter Rosin <peda@axentia.se>
13 Define what GPIO pins are used to control a multiplexer. Or several
14 multiplexers, if the same pins control more than one multiplexer.
22 const: gpio-mux
24 mux-gpios:
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Dmux-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/mux-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
14 that uses the mux controller. Thus, a mux controller can possibly control
17 control several multiplexers for a single consumer.
20 space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer,
21 0-7 for an 8-way multiplexer, etc.
25 --------------------
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/Linux-v6.1/include/linux/firmware/imx/svc/
Dpm.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2017-2018 NXP
8 * control, clock control, reset control, and wake-up event control.
56 #define IMX_SC_PM_PW_MODE_LP 2 /* Power in low-power */
77 * Defines for SC PM CLK Parent
79 #define IMX_SC_PM_PARENT_XTAL 0 /* Parent is XTAL. */
80 #define IMX_SC_PM_PARENT_PLL0 1 /* Parent is PLL0 */
81 #define IMX_SC_PM_PARENT_PLL1 2 /* Parent is PLL1 or PLL0/2 */
82 #define IMX_SC_PM_PARENT_PLL2 3 /* Parent in PLL2 or PLL0/4 */
83 #define IMX_SC_PM_PARENT_BYPS 4 /* Parent is a bypass clock. */
/Linux-v6.1/include/linux/
Dwwan.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 * enum wwan_port_type - WWAN port types
14 * @WWAN_PORT_MBIM: Mobile Broadband Interface Model control
15 * @WWAN_PORT_QMI: Qcom modem/MSM interface for modem control
33 WWAN_PORT_MAX = __WWAN_PORT_MAX - 1,
43 /** struct wwan_port_ops - The WWAN port operations
46 * @tx: Non-blocking routine that sends WWAN port protocol data to the device.
51 * The wwan_port_ops structure contains a list of low-level operations
52 * that control a WWAN port device. All functions are mandatory unless specified.
66 * wwan_create_port - Add a new WWAN port
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Dpowercap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
24 * struct powercap_control_type_ops - Define control type callbacks
25 * @set_enable: Enable/Disable whole control type.
32 * control type is closed. So it is safe to free data
33 * structure associated with this control type.
35 * for the control type.
37 * This structure defines control type callbacks to be implemented by client
47 * struct powercap_control_type - Defines a powercap control_type
52 * @lock: mutex for control type
58 * @node: linked-list node
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/Linux-v6.1/drivers/acpi/acpica/
Dpsparse.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: psparse - Parser top level AML parse routines
6 * Copyright (C) 2000 - 2022, Intel Corp.
34 * PARAMETERS: opcode - An AML opcode
44 /* Extended (2-byte) opcode if > 255 */ in acpi_ps_get_opcode_size()
59 * PARAMETERS: parser_state - A parser state object
72 aml = parser_state->aml; in acpi_ps_peek_opcode()
90 * PARAMETERS: walk_state - Current State
91 * op - Op to complete
121 if (((walk_state->parse_flags & ACPI_PARSE_TREE_MASK) != in acpi_ps_complete_this_op()
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/Linux-v6.1/drivers/infiniband/hw/qib/
Dqib_pcie.c2 * Copyright (c) 2010 - 2017 Intel Corporation. All rights reserved.
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
51 * from qib_pcie_params, which every chip-specific
82 qib_early_err(&pdev->dev, "pci enable failed: error %d\n", in qib_pcie_init()
83 -ret); in qib_pcie_init()
89 qib_devinfo(pdev, "pci_request_regions fails: err %d\n", -ret); in qib_pcie_init()
93 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in qib_pcie_init()
100 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in qib_pcie_init()
110 qib_early_err(&pdev->dev, in qib_pcie_init()
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/Linux-v6.1/drivers/regulator/
Dtps65090-regulator.c1 // SPDX-License-Identifier: GPL-2.0-only
33 * struct tps65090_regulator - Per-regulator data for a tps65090 regulator
54 * tps65090_reg_set_overcurrent_wait - Setup overcurrent wait
62 * Return: 0 if no error, non-zero if there was an error writing the register.
69 ret = regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, in tps65090_reg_set_overcurrent_wait()
71 ri->overcurrent_wait << CTRL_WT_BIT); in tps65090_reg_set_overcurrent_wait()
73 dev_err(&rdev->dev, "Error updating overcurrent wait %#x\n", in tps65090_reg_set_overcurrent_wait()
74 rdev->desc->enable_reg); in tps65090_reg_set_overcurrent_wait()
81 * tps65090_try_enable_fet - Try to enable a FET
85 * Return: 0 if ok, -ENOTRECOVERABLE if the FET power good bit did not get
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/Linux-v6.1/drivers/hid/
Dhid-roccat-koneplus.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 * and functionality and without the non-standard behaviours the Kone had.
22 #include <linux/hid-roccat.h>
23 #include "hid-ids.h"
24 #include "hid-roccat-common.h"
25 #include "hid-roccat-koneplus.h"
34 koneplus->actual_profile = new_profile; in koneplus_profile_activated()
40 struct roccat_common2_control control; in koneplus_send_control() local
45 return -EINVAL; in koneplus_send_control()
47 control.command = ROCCAT_COMMON_COMMAND_CONTROL; in koneplus_send_control()
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Dhid-roccat-kovaplus.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include <linux/hid-roccat.h>
21 #include "hid-ids.h"
22 #include "hid-roccat-common.h"
23 #include "hid-roccat-kovaplus.h"
37 if (new_profile_index >= ARRAY_SIZE(kovaplus->profile_settings)) in kovaplus_profile_activated()
39 kovaplus->actual_profile = new_profile_index; in kovaplus_profile_activated()
40 kovaplus->actual_cpi = kovaplus->profile_settings[new_profile_index].cpi_startup_level; in kovaplus_profile_activated()
41 kovaplus->actual_x_sensitivity = kovaplus->profile_settings[new_profile_index].sensitivity_x; in kovaplus_profile_activated()
42 kovaplus->actual_y_sensitivity = kovaplus->profile_settings[new_profile_index].sensitivity_y; in kovaplus_profile_activated()
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Dhid-roccat-pyra.c1 // SPDX-License-Identifier: GPL-2.0-or-later
22 #include <linux/hid-roccat.h>
23 #include "hid-ids.h"
24 #include "hid-roccat-common.h"
25 #include "hid-roccat-pyra.h"
35 if (new_profile >= ARRAY_SIZE(pyra->profile_settings)) in profile_activated()
37 pyra->actual_profile = new_profile; in profile_activated()
38 pyra->actual_cpi = pyra->profile_settings[pyra->actual_profile].y_cpi; in profile_activated()
44 struct roccat_common2_control control; in pyra_send_control() local
49 return -EINVAL; in pyra_send_control()
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Dhid-roccat-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include "hid-roccat-common.h"
29 return -ENOMEM; in roccat_common2_receive()
39 return ((len < 0) ? len : ((len != size) ? -EIO : 0)); in roccat_common2_receive()
51 return -ENOMEM; in roccat_common2_send()
60 return ((len < 0) ? len : ((len != size) ? -EIO : 0)); in roccat_common2_send()
75 struct roccat_common2_control control; in roccat_common2_receive_control_status() local
81 &control, sizeof(struct roccat_common2_control)); in roccat_common2_receive_control_status()
86 switch (control.value) { in roccat_common2_receive_control_status()
95 return -EINVAL; in roccat_common2_receive_control_status()
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/Linux-v6.1/drivers/clk/bcm/
Dclk-kona-setup.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include "clk-kona.h"
13 #define selector_clear_exists(sel) ((sel)->width = 0)
20 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
23 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
26 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid()
29 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
32 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid()
33 pr_err("%s: bad policy control offset for %s " in ccu_data_offsets_valid()
35 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid()
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Dclk-kona.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
20 /* The common clock framework uses u8 to represent a parent index */
24 #define BAD_CLK_NAME ((const char *)-1)
33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
44 #define policy_exists(policy) ((policy)->offset != 0)
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Dclk-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
27 /* Produces a mask of set bits covering a range of a 32-bit value */
30 return ((1 << width) - 1) << shift; in bitfield_mask()
52 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
68 combined <<= div->u.s.frac_width; in scaled_div_build()
78 return (u64)div->u.fixed; in scaled_div_min()
89 return (u64)div->u.fixed; in scaled_div_max()
91 reg_div = ((u32)1 << div->u.s.width) - 1; in scaled_div_max()
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/Linux-v6.1/drivers/usb/common/
Dulpi.c1 // SPDX-License-Identifier: GPL-2.0
3 * ulpi.c - USB ULPI PHY bus
19 #include <linux/clk/clk-conf.h>
21 /* -------------------------------------------------------------------------- */
25 return ulpi->ops->read(ulpi->dev.parent, addr); in ulpi_read()
31 return ulpi->ops->write(ulpi->dev.parent, addr, val); in ulpi_write()
35 /* -------------------------------------------------------------------------- */
47 if (ulpi->id.vendor == 0 || !drv->id_table) in ulpi_match()
50 for (id = drv->id_table; id->vendor; id++) in ulpi_match()
51 if (id->vendor == ulpi->id.vendor && in ulpi_match()
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/Linux-v6.1/drivers/irqchip/
Dirq-al-fic.c1 // SPDX-License-Identifier: GPL-2.0
50 u32 control = readl_relaxed(fic->base + AL_FIC_CONTROL); in al_fic_set_trigger() local
54 control &= ~CONTROL_TRIGGER_RISING; in al_fic_set_trigger()
57 control |= CONTROL_TRIGGER_RISING; in al_fic_set_trigger()
59 gc->chip_types->handler = handler; in al_fic_set_trigger()
60 fic->state = new_state; in al_fic_set_trigger()
61 writel_relaxed(control, fic->base + AL_FIC_CONTROL); in al_fic_set_trigger()
67 struct al_fic *fic = gc->private; in al_fic_irq_set_type()
76 ret = -EINVAL; in al_fic_irq_set_type()
92 if (fic->state == AL_FIC_UNCONFIGURED) { in al_fic_irq_set_type()
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/Linux-v6.1/Documentation/devicetree/bindings/clock/ti/
Dmux.txt3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped multiplexer with multiple input clock signals or
8 gate or adjust the parent rate via a divider or multiplier.
17 register value selected parent clock
24 "index-starts-at-one" modified the scheme as follows:
26 register value selected clock parent
31 The binding must provide the register to control the mux. Optionally
32 the number of bits to shift the control field in the register can be
36 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
39 - compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
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/Linux-v6.1/drivers/mfd/
Dtc6393xb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright(c) 2005-2006 Chris Humbert
39 #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
40 #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
41 #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
42 #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
43 #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
44 #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
45 #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
46 #define SCR_CCR 0x98 /* w Clock Control */
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/Linux-v6.1/drivers/clk/ingenic/
Dcgu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2013-2015 Imagination Technologies
13 #include <linux/clk-provider.h>
18 * struct ingenic_cgu_pll_info - information about a PLL
19 * @reg: the offset of the PLL's control register within the CGU
23 * control register)
25 * @m_offset: the multiplier value which encodes to 0 in the PLL's control
29 * control register)
31 * @n_offset: the divider value which encodes to 0 in the PLL's control
33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
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