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/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dsamsung,s5pv210-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5P6442/S5PC110/S5PV210 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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Dsamsung,exynos-ext-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos-ext-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC external/osc/XXTI/XusbXTI clock
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Samsung SoCs require an external clock supplied through XXTI or XusbXTI pins.
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Dsamsung,s5pv210-audss-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-audss-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5Pv210 SoC Audio SubSystem clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
17 include/dt-bindings/clock/s5pv210-audss.h header.
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Dsamsung,exynos5410-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5410-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5410 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
[all …]
Dsamsung,exynos5433-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5433-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5433 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
[all …]
Dsamsung,exynos7-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos7 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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/Linux-v6.1/arch/arm64/boot/dts/exynos/
Dexynos5433.dtsi1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
24 interrupt-parent = <&gic>;
26 arm-a53-pmu {
27 compatible = "arm,cortex-a53-pmu";
32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
35 arm-a57-pmu {
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/Linux-v6.1/arch/arm/boot/dts/
Ds5pv210.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
19 #include <dt-bindings/clock/s5pv210.h>
20 #include <dt-bindings/clock/s5pv210-audss.h>
23 #address-cells = <1>;
24 #size-cells = <1>;
45 #address-cells = <1>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a8";
55 xxti: oscillator-0 { label
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Dexynos4412-tiny4412.dts1 // SPDX-License-Identifier: GPL-2.0
11 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/leds/common.h>
21 stdout-path = &serial_0;
30 compatible = "gpio-leds";
36 default-state = "off";
37 linux,default-trigger = "heartbeat";
43 default-state = "off";
49 default-state = "off";
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Dexynos4412-smdk4412.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
12 /dts-v1/;
14 #include "exynos-mfc-reserved-memory.dtsi"
27 stdout-path = "serial1:115200n8";
30 fixed-rate-clocks {
31 xxti {
32 compatible = "samsung,clock-xxti";
33 clock-frequency = <0>;
37 compatible = "samsung,clock-xusbxti";
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Dexynos4210-smdkv310.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
14 /dts-v1/;
16 #include <dt-bindings/gpio/gpio.h>
17 #include "exynos-mfc-reserved-memory.dtsi"
30 stdout-path = "serial1:115200n8";
33 fixed-rate-clocks {
34 xxti {
35 compatible = "samsung,clock-xxti";
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Dexynos4210-origen.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
14 /dts-v1/;
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/leds/common.h>
19 #include "exynos-mfc-reserved-memory.dtsi"
35 stdout-path = "serial2:115200n8";
38 mmc_reg: voltage-regulator {
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Dexynos5260-xyref5260.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
22 stdout-path = "serial2:115200n8";
25 fin_pll: xxti {
26 compatible = "fixed-clock";
27 clock-frequency = <24000000>;
28 clock-output-names = "fin_pll";
29 #clock-cells = <0>;
32 ioclk_pcm: clock-pcm-ext {
33 compatible = "fixed-clock";
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Dexynos5250-smdk5250.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/clock/maxim,max77686.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
29 stdout-path = "serial2:115200n8";
32 vdd: fixed-regulator-vdd {
33 compatible = "regulator-fixed";
34 regulator-name = "vdd-supply";
35 regulator-min-microvolt = <1800000>;
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Dexynos5410-smdk5410.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/irq.h>
22 stdout-path = "serial2:115200n8";
25 fin_pll: xxti {
26 compatible = "fixed-clock";
27 clock-frequency = <24000000>;
28 clock-output-names = "fin_pll";
29 #clock-cells = <0>;
32 pmic_ap_clk: pmic-ap-clk {
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Dexynos4412-odroid-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards
7 #include <dt-bindings/sound/samsung-i2s.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
11 #include "exynos4412-ppmu-common.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include "exynos-mfc-reserved-memory.dtsi"
17 stdout-path = &serial_1;
21 compatible = "samsung,secure-firmware";
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Dexynos4210-trats.dts1 // SPDX-License-Identifier: GPL-2.0
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
19 chassis-type = "handset";
31 stdout-path = "serial2:115200n8";
34 vemmc_reg: regulator-0 {
35 compatible = "regulator-fixed";
36 regulator-name = "VMEM_VDD_2.8V";
37 regulator-min-microvolt = <2800000>;
38 regulator-max-microvolt = <2800000>;
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Dexynos4412-itop-scp-core.dtsi1 // SPDX-License-Identifier: GPL-2.0
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
17 #include "exynos4412-ppmu-common.dtsi"
18 #include "exynos-mfc-reserved-memory.dtsi"
27 compatible = "samsung,secure-firmware";
31 fixed-rate-clocks {
32 xxti {
33 compatible = "samsung,clock-xxti";
[all …]
Dexynos4412-origen.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
12 /dts-v1/;
14 #include <dt-bindings/clock/samsung,s2mps11.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
17 #include "exynos-mfc-reserved-memory.dtsi"
29 stdout-path = "serial2:115200n8";
33 compatible = "samsung,secure-firmware";
37 mmc_reg: regulator-0 {
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Dexynos5250-spring.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/input/input.h>
19 chassis-type = "laptop";
28 stdout-path = "serial3:115200n8";
31 gpio-keys {
32 compatible = "gpio-keys";
[all …]
/Linux-v6.1/drivers/clk/samsung/
Dclk-s5pv210-audss.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on Exynos Audio Subsystem Clock Controller driver:
10 * Driver for Audio Subsystem Clock Controller of S5PV210-compatible SoCs.
15 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/s5pv210-audss.h>
76 clk_data = devm_kzalloc(&pdev->dev, in s5pv210_audss_clk_probe()
81 return -ENOMEM; in s5pv210_audss_clk_probe()
83 clk_data->num = AUDSS_MAX_CLKS; in s5pv210_audss_clk_probe()
84 clk_table = clk_data->hws; in s5pv210_audss_clk_probe()
86 hclk = devm_clk_get(&pdev->dev, "hclk"); in s5pv210_audss_clk_probe()
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Dclk-s5pv210.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Based on clock drivers for S3C64xx and Exynos4 SoCs.
8 * Common Clock Framework support for all S5PC110/S5PV210 SoCs.
11 #include <linux/clk-provider.h>
16 #include "clk-pll.h"
18 #include <dt-bindings/clock/s5pv210.h>
20 /* S5PC110/S5PV210 clock controller register offsets */
76 xxti, enumerator
130 "xxti",
167 "xxti",
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Dclk-exynos4.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Common Clock Framework support for all Exynos4 SoCs.
10 #include <dt-bindings/clock/exynos4.h>
13 #include <linux/clk-provider.h>
19 #include "clk-cpu.h"
21 /* Exynos4 clock controller register offsets */
278 /* list of all parent clock list */
295 /* Exynos 4210-specific parent groups */
299 PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m",
303 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
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Dclk-exynos5410.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Common Clock Framework support for Exynos5410 SoC.
9 #include <dt-bindings/clock/exynos5410.h>
11 #include <linux/clk-provider.h>
269 struct clk *xxti = of_clk_get(np, 0); in exynos5410_clk_init() local
271 if (!IS_ERR(xxti) && clk_get_rate(xxti) == 24 * MHZ) in exynos5410_clk_init()
276 pr_debug("Exynos5410: clock setup completed.\n"); in exynos5410_clk_init()
278 CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
/Linux-v6.1/Documentation/devicetree/bindings/display/samsung/
Dsamsung,exynos-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,exynos4210-hdmi
19 - samsung,exynos4212-hdmi
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