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/Linux-v5.15/Documentation/devicetree/bindings/memory-controllers/
Dti-aemif.txt1 * Device tree bindings for Texas instruments AEMIF controller
4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
[all …]
Darm,pl172.txt1 * Device tree bindings for ARM PL172/PL175/PL176 MultiPort Memory Controller
5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
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/Linux-v5.15/Documentation/devicetree/bindings/clock/ti/
Ddra7-atl.txt1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
3 The ATL IP is used to generate clock to be used to synchronize baseband and
4 audio codec. A single ATL IP provides four ATL clock instances sharing the same
5 functional clock but can be configured to provide different clocks.
6 ATL can maintain a clock averages to some desired frequency based on the bws/aws
7 signals - can compensate the drift between the two ws signal.
12 Clock tree binding:
13 This binding uses the common clock binding[1].
14 To be able to integrate the ATL clocks with DT clock tree.
16 Since the clock instances are part of a single IP this binding is used as a node
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/Linux-v5.15/Documentation/devicetree/bindings/display/bridge/
Dsnps,dw-mipi-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/snps,dw-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Philippe CORNU <philippe.cornu@st.com>
13 This document defines device tree properties for the Synopsys DesignWare MIPI
14 DSI host controller. It doesn't constitue a device tree binding specification
15 by itself but is meant to be referenced by platform-specific device tree
18 When referenced from platform device tree bindings the properties defined in
19 this document are defined as follows. The platform device tree bindings are
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Dsynopsys,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 This document defines device tree properties for the Synopsys DesignWare HDMI
14 TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
15 binding specification by itself but is meant to be referenced by device tree
16 bindings for the platform-specific integrations of the DWC HDMI TX.
18 When referenced from platform device tree bindings the properties defined in
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Dtoshiba,tc358767.txt4 - compatible: "toshiba,tc358767"
5 - reg: i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins
6 - clock-names: should be "ref"
7 - clocks: OF device-tree clock specification for refclk input. The reference
8 clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz.
11 - shutdown-gpios: OF device-tree gpio specification for SD pin
13 - reset-gpios: OF device-tree gpio specification for RSTX pin
15 - toshiba,hpd-pin: TC358767 GPIO pin number to which HPD is connected to (0 or 1)
16 - ports: the ports node can contain video interface port nodes to connect
18 - port@0: DSI input port
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/Linux-v5.15/drivers/clk/sunxi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "Legacy clock support for Allwinner SoCs"
10 bool "Legacy clock drivers"
13 Legacy clock drivers being used on older (A10, A13, A20,
15 Device Tree backward compatibility issues, in case one would
16 still use a Device Tree with one clock provider by
25 Legacy clock driver for the A31 PRCM clocks. Those are
33 Legacy clock driver for the sun8i family PRCM clocks.
41 Legacy clock driver for the A80 PRCM clocks. Those are
/Linux-v5.15/Documentation/devicetree/bindings/clock/
Dexynos7-clock.txt1 * Samsung Exynos7 Clock Controller
3 Exynos7 clock controller has various blocks which are instantiated
4 independently from the device-tree. These clock controllers
8 Each clock is assigned an identifier and client nodes can use
9 this identifier to specify the clock which they consume. All
11 dt-bindings/clock/exynos7-clk.h header and can be used in
12 device tree sources.
17 is expected that they are defined using standard clock bindings
18 with following clock-output-names:
20 - "fin_pll" - PLL input clock from XXTI
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Damlogic,meson8b-clkc.txt1 * Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
3 The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
4 supplies clock to various controllers within the SoC.
8 - compatible: must be one of:
9 - "amlogic,meson8-clkc" for Meson8 (S802) SoCs
10 - "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
11 - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
14 - clocks: list of clock phandles, one for each entry in clock-names
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Dsamsung,s5pv210-clock.txt1 * Samsung S5P6442/S5PC110/S5PV210 Clock Controller
3 Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock
4 controller, which generates and supplies clock to various controllers
9 - compatible: should be one of following:
10 - "samsung,s5pv210-clock" : for clock controller of Samsung
12 - "samsung,s5p6442-clock" : for clock controller of Samsung
15 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
21 dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
26 that they are defined using standard clock bindings with following
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Drockchip,rk3288-cru.txt1 * Rockchip RK3288 Clock and Reset Unit
3 The RK3288 clock controller generates and supplies clock to various
7 A revision of this SoC is available: rk3288w. The clock tree is a bit
8 different so another dt-compatible is available. Noticed that it is only
14 - compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in
16 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
19 - #reset-cells: should be 1.
23 - rockchip,grf: phandle to the syscon managing the "general register files"
26 Each clock is assigned an identifier and client nodes can use this identifier
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Dxlnx,zynqmp-clk.txt1 --------------------------------------------------------------------------
2 Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
4 --------------------------------------------------------------------------
5 The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
6 tree. It reads required input clock frequencies from the devicetree and acts
7 as clock provider for all clock consumers of PS clocks.
9 See clock_bindings.txt for more information on the generic clock bindings.
12 - #clock-cells: Must be 1
13 - compatible: Must contain: "xlnx,zynqmp-clk"
14 - clocks: List of clock specifiers which are external input
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Dsamsung,s2mps11.txt1 Binding for Samsung S2M and S5M family clock generator block
4 This is a part of device tree bindings for S2M and S5M family multi-function
6 More information can be found in bindings/mfd/sec-core.txt file.
11 To register these as clocks with common clock framework instantiate under
12 main device node a sub-node named "clocks".
14 It uses the common clock binding documented in:
15 - Documentation/devicetree/bindings/clock/clock-bindings.txt
18 Required properties of the "clocks" sub-node:
19 - #clock-cells: should be 1.
20 - compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps13-clk",
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Dst,nomadik.txt3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 PLLs and clock gates.
10 - compatible: must be "stericsson,nomadik-src"
11 - reg: must contain the SRC register base and size
14 - disable-sxtalo: if present this will disable the SXTALO
17 - disable-mxtal: if present this will disable the MXTALO,
25 fixed frequency clock, as parent.
28 - compatible: must be "st,nomadik-pll-clock"
29 - clock-cells: must be 0
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Dclock-bindings.txt1 This binding is a work-in-progress, and are based on some experimental
4 Sources of clock signal can be represented by any node in the device
5 tree. Those nodes are designated as clock providers. Clock consumer
6 nodes use a phandle and clock specifier pair to connect clock provider
7 outputs to clock inputs. Similar to the gpio specifiers, a clock
8 specifier is an array of zero, one or more cells identifying the clock
9 output on a device. The length of a clock specifier is defined by the
10 value of a #clock-cells property in the clock provider node.
14 ==Clock providers==
17 #clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
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Damlogic,gxbb-aoclkc.txt1 * Amlogic GXBB AO Clock and Reset Unit
3 The Amlogic GXBB AO clock controller generates and supplies clock to various
4 controllers within the Always-On part of the SoC.
8 - compatible: value should be different for each SoC family as :
9 - GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
10 - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
11 - GXM (S912) : "amlogic,meson-gxm-aoclkc"
12 - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
13 - G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc"
14 followed by the common "amlogic,meson-gx-aoclkc"
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Dzynq-7000.txt1 Device Tree Clock bindings for the Zynq 7000 EPP
6 See clock_bindings.txt for more information on the generic clock bindings.
9 == Clock Controller ==
10 The clock controller is a logical abstraction of Zynq's clock tree. It reads
11 required input clock frequencies from the devicetree and acts as clock provider
12 for all clock consumers of PS clocks.
15 - #clock-cells : Must be 1
16 - compatible : "xlnx,ps7-clkc"
17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
18 - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
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Drenesas,emev2-smu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
15 This is not a clock provider, but clocks under SMU depend on it.
19 const: renesas,emev2-smu
24 '#address-cells':
27 '#size-cells':
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/Linux-v5.15/Documentation/devicetree/bindings/display/
Ddsi-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/dsi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 This document defines device tree properties common to DSI, Display
15 a device tree binding specification by itself but is meant to be referenced
16 by device tree bindings.
18 When referenced from panel device tree bindings the properties defined in
19 this document are defined as follows. The panel device tree bindings are
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/Linux-v5.15/Documentation/devicetree/bindings/media/i2c/
Dovti,ov02a10.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Omnivision OV02A10 CMOS Sensor Device Tree Bindings
11 - Dongchun Zhu <dongchun.zhu@mediatek.com>
13 description: |-
14 The Omnivision OV02A10 is a low-cost, high performance, 1/5-inch, 2 megapixel
17 @ 1600x1200 (UXGA) resolution transferred over a 1-lane MIPI interface. The
18 sensor output is available via CSI-2 serial data output.
21 - $ref: /schemas/media/video-interface-devices.yaml#
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/Linux-v5.15/drivers/clk/keystone/
Dpll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PLL clock driver for Keystone devices
6 * Murali Karicheri <m-karicheri2@ti.com>
9 #include <linux/clk-provider.h>
26 * struct clk_pll_data - pll data structure
28 * register of pll controller, else it is in the pll_ctrl0((bit 11-6)
64 * struct clk_pll - Main pll clock
79 struct clk_pll_data *pll_data = pll->pll_data; in clk_pllclk_recalc()
84 * get bits 0-5 of multiplier from pllctrl PLLM register in clk_pllclk_recalc()
87 if (pll_data->has_pllctrl) { in clk_pllclk_recalc()
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/Linux-v5.15/Documentation/devicetree/bindings/pwm/
Dpwm-fsl-ftm.txt4 device tree provides a property to describing this so that an operating system
8 SoC | FTM-PWM endianness
9 --------+-------------------
15 modes in device tree.
19 - compatible : should be "fsl,<soc>-ftm-pwm" and one of the following
21 - "fsl,vf610-ftm-pwm" for PWM compatible with the one integrated on VF610
22 - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM
23 - reg: Physical base address and length of the controller's registers
24 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
26 - clock-names: Should include the following module clock source entries:
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Ds5pv210-smdkc110.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's S5PV210 SoC device tree source
5 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
10 * Board device tree source for YIC System SMDC110 board.
12 * NOTE: This file is completely based on original board file for mach-smdkc110
17 /dts-v1/;
18 #include <dt-bindings/input/input.h>
34 pmic_ap_clk: clock-0 {
35 /* Workaround for missing PMIC and its clock */
36 compatible = "fixed-clock";
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Ds3c6410-smdk6410.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung S3C6410 based SMDK6410 board device tree source.
7 * Device tree source file for Samsung SMDK6410 board which is based on
11 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
31 fin_pll: oscillator-0 {
32 compatible = "fixed-clock";
33 clock-frequency = <12000000>;
34 clock-output-names = "fin_pll";
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/Linux-v5.15/arch/powerpc/platforms/512x/
Dclock-commonclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * common clock driver support for the MPC512x platform
12 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/mpc512x-clock.h>
69 /* data required for the OF clock provider registration */
89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
90 * those differences can get folded into this clock provider support
292 val &= (1 << len) - 1; in get_bit_field()
305 spmf = get_bit_field(&clkregs->spmr, 24, 4); in get_spmf_mult()
326 divcode = get_bit_field(&clkregs->scfr2, 26, 6); in get_sys_div_x2()
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